UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 532

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
The following problem may occur when long pulse width is measured in the free-running timer mode.
<1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TT0CCRn register.
Remark
TT0CCRn register
INTTT0OV signal
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
(incorrect).
Actually, the pulse width must be (20000H + D
TIT0n pin input
16-bit counter
TT0OVF bit
Example of incorrect processing when capture trigger interval is long
n = 0, 1
TT0CE bit
FFFFH
0000H
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
D
a0
<1> <2>
a1
− D
1 cycle of 16-bit counter
a0
) because an overflow occurs twice.
Pulse width
D
a0
<3> <4>
D
a1
D
a1
Page 532 of 1509
a1
− D
a0
)