UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 674

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Real-time output buffer registers 0L, 0H (RTBL0, RTBH0)
Note After setting the real-time output port, set output data to the RTBL0 and RTBH0 registers by the time a real-time
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
The RTBL0 and RTBH0 registers are 4-bit registers that hold output data in advance.
These registers are each mapped to independent addresses in the peripheral I/O register area.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
If an operation mode of 4 bits × 1 channel or 2 bits × 1 channel is specified (RTPC0.BYTE0 bit = 0), data can be
individually set to the RTBL0 and RTBH0 registers. The data of both these registers can be read at once by
specifying the address of either of these registers.
If an operation mode of 6 bits × 1 channel is specified (BYTE0 bit = 1), 8-bit data can be set to both the RTBL0 and
RTBH0 registers by writing the data to either of these registers. Moreover, the data of both these registers can be
read at once by specifying the address of either of these registers.
Table 14-2 shows the operation when the RTBL0 and RTBH0 registers are manipulated.
output trigger is generated.
Operation Mode
RTBL0
RTBH0
Cautions 1. When writing to bits 6 and 7 of the RTBH0 register, always set 0.
After reset: 00H
Table 14-2. Operation During Manipulation of RTBL0 and RTBH0 Registers
2. Accessing the RTBL0 and RTBH0 registers is prohibited in the following
RTBL0
RTBH0
RTBL0
RTBH0
0
Register to Be
Manipulated
statuses. For details, see 3.4.9 (2) Accessing specific on-chip peripheral I/O
registers.
• When the CPU operates on the subclock and the main clock oscillation is
• When the CPU operates on the internal oscillation clock
stopped
R/W
0
Address: RTBL0 FFFFF6E0H, RTBH0 FFFFF6E2H
RTBH05 RTBH04
RTBH0
RTBH0
RTBH0
RTBH0
Higher 4 Bits
CHAPTER 14 REAL-TIME OUTPUT FUNCTION (RTO)
Read
RTBL0
RTBL0
RTBL0
RTBL0
RTBL03 RTBL02
Lower 4 Bits
Invalid
RTBH0
RTBH0
RTBH0
Higher 4 Bits
RTBL01
RTBL00
Write
Note
RTBL0
RTBL0
RTBL0
Invalid
Lower 4 Bits
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