UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 503

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOT01 pin. After the one-
shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger. When the trigger is
generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is
being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTT0CC1) is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
used as the trigger.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TT0CE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the 16-bit
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
The valid edge of an external trigger input (EVTT0 pin) or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is
External trigger input
Output delay period = (Set value of TT0CCR1 register) × Count clock cycle
Active level width = (Set value of TT0CCR0 register − Set value of TT0CCR1 register + 1) × Count clock cycle
INTTT0CC0 signal
INTTT0CC1 signal
TT0CCR0 register
TT0CCR1 register
(EVTT0 pin input)
TOT00 pin output
TOT01 pin output
16-bit counter
TT0CE bit
FFFFH
0000H
Figure 9-26. Basic Timing in One-Shot Pulse Output Mode
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
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