UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 211

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Lock register (LOCKR)
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear
[Set conditions]
[Clear conditions]
• Upon system reset
• In IDLE2 or STOP mode
• Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
• Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of
• Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 25.2
• Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release,
• Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed
• After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register)
Phase lock occurs at a given frequency following power application or immediately after the STOP mode is
released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until
stabilization is called the lockup status, and the stabilized state is called the locked status.
The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
PCC.MCK bit to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
(3) Oscillation stabilization time select register (OSTS)))
when the STOP mode was set in the PLL operating status
from 0 to 1
when the IDLE2 mode is set during PLL operation.
conditions are as follows.
oscillation stabilization time has elapsed.
LOCKR
After reset: 00H
Note
LOCK
0
1
0
Locked status
Unlocked status
R
0
Address: FFFFF824H
0
0
PLL lock status check
CHAPTER 6 CLOCK GENERATION FUNCTION
0
0
0
LOCK
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