UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 631

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
11.4.6 A/D conversion start trigger output function
INTTAA4CC0, INTTAA4CC1) to generate the A/D conversion start trigger signal (TABTADT0).
or more trigger sources can be specified at the same time.
TAB1OPT1.TAB1ICE and TAB1OPT1.TAB1IOE bits), the A/D conversion start trigger signal is not output.
trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the TAB1AT2 and TAB1AT3
bits.
sets the A/D conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflected
in the output status of the A/D conversion start trigger signal. These control bits do not have a transfer function and can be
used only in the anytime rewrite mode.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The V850ES/JG3-H and V850ES/JH3-H have a function to select four trigger sources (INTTAB1OV, INTTAB1CC0,
The trigger sources are specified by the TAB1OPT2.TAB1AT0 to TAB1OPT2.TAB1AT3 bits.
• TAB1AT0 bit = 1:
• TAB1AT1 bit = 1:
• TAB1AT2 bit = 1:
• TAB1AT3 bit = 1:
The A/D conversion start trigger signals selected by the TAB1AT0 to TAB1AT3 bits are ORed and output. Therefore, two
The INTTAB1OV and INTTAB1CC0 signals selected by the TAB1AT0 and TAB1AT1 bits are culled interrupt signals.
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the
The trigger sources (INTTAA4CC0 and INTTAA4CC1) from TAA4 have a function to mask the A/D conversion start
• TAB1ATM2 bit: Corresponds to the TAB1AT2 bit and controls INTTAA4CC0 (match interrupt signal) of TAA4.
• TAB1ATM3 bit: Corresponds to the TAB1AT3 bit and controls INTTAA4CC1 (match interrupt signal) of TAA4.
The TAB1ATM3, TAB1ATM2, and TAB1AT3 to TAB1AT0 bits can be rewritten while the timer is operating. If the bit that
• TAB1ATM2 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
• TAB1ATM2 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
• TAB1ATM3 bit = 0: The A/D conversion start trigger signal is output when the 16-bit counter counts up
• TAB1ATM3 bit = 1: The A/D conversion start trigger signal is output when the 16-bit counter counts up
A/D conversion start trigger signal generated when INTTAB1OV (counter underflow) occurs.
A/D conversion start trigger signal generated when INTTAB1CC0 (cycle match) occurs.
A/D conversion start trigger signal generated when INTTAA4CC0 (match of TAA4CCR0 register of TAA4 during
tuning operation) occurs.
A/D conversion start trigger signal generated when INTTAA4CC1 (match of TAA4CCR1 register of TAA4 during
tuning operation) occurs.
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
(TAB1OPT0.TAB1CUF bit = 0), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 1).
(TAB1OPT0.TAB1CUF bit = 1), and the A/D conversion start trigger signal is not output when
the 16-bit counter counts down (TAB1OPT0.TAB1CUF bit = 0).
CHAPTER 11 MOTOR CONTROL FUNCTION
Page 631 of 1509

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