UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1423

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
33.7.2 Bus timing
(T
Remarks 1. t
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Delay time from RD↓ to address float
Data input setup time from address
Data input setup time from RD↓
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WRm↓
Data input hold time (from RD↑)
Address output delay time from RD↑
Delay time from RD↑ to ASTB↑
Delay time from WRm↑ to ASTB↑
Delay time from RD↑ to ASTB↓
RD low-level width
WRm low-level width
ASTB high-level width
Data output delay time from WRm↓
Data output delay time (from WRm↑)
Data output hold time (from WRm↑)
WAIT setup time (to address)
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
Address hold time from RD↑
Address hold time from WRm↑
Hold time from RD↑ to CSn
Hold time from WRm↑ to CSn
A
(1) In multiplexed bus mode/separate bus mode
= −40 to +85°C, V
(a) Read/write cycle (CLKOUT asynchronous)
2. T = 1/f
3. n: Number of wait clocks inserted in the bus cycle
4. m = 0, 1
5. i: Number of idle states inserted after a read cycle (0 or 1)
6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Parameter
t
The sampling timing changes when a programmable wait is inserted.
ASW
AHW
: Number of address setup wait clocks
: Number of address hold wait clocks
CPU
DD
(f
= EV
CPU
: CPU operating clock frequency)
DD
= UV
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DAST
HSTA
FRDA
DAID
DRDID2
DSTRD
DSTWR
HRDID
DRDOD
DRDST
DWRST
DRDST
WRDL
WWRL
WSTH
DWROD
DODWR
HWROD
SAWT1
SAWT2
HAWT1
HAWT2
SSTWT1
SSTWT2
HSTWT1
HSTWT2
HRDA2
HWRA2
HRDC2
HWRC2
DD
Symbol
= AV
<6>
<7>
<8>
<9>
<10>
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
REF0
= AV
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
i ≥ 1
Conditions
REF1
, V
SS
(0.5 + t
(0.5 + t
(0.5 + t
0
(1 + i)T − 3
0.5T − 5
(1.5 + i + t
(1 + n)T − 10
(1 + i + t
(1 + n)T − 11
T − 3
(0.5 + n + t
(1.5 + n + t
(n + t
(1 + n + t
(1 + i)T − 5
T − 5
T − 5
T − 5
= AV
CHAPTER 33 ELECTRICAL SPECIFICATIONS
AHw
ASw
AHw
AHw
SS
)T
ASw
AHw
)T − 9
)T − 8
)T − 4
ASw
MIN.
= 0 V, C
ASw
ASw
)T − 10
)T
)T − 4
+ t
+ t
AHw
AHw
L
)T
)T
= 50 pF)
5
(2 + n + t
(1 + n)T − 15
9
(1.5 + t
(1.5 + n + t
(1 + t
(1 + n + t
AHw
ASw
)T − 15
ASw
AHw
+ t
ASw
MAX.
)T − 15
+ t
AHw
+ t
AHw
)T − 25
AHw
)T − 25
Page 1423 of 1509
)T − 25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit