SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 21

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.4
The TC1736 32-Bit Single-Chip Microcontroller offers several versatile on-chip system
peripheral units such as DMA controller, embedded Flash module, interrupt system and
ports.
2.4.1
The TC1736 includes a programmable interrupt system with the following features:
Features
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2.4.2
The TC1736 includes a fast and flexible DMA controller with 8 independent DMA
channels (one DMA engine).
Features
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Data Sheet
Fast interrupt response
Hardware arbitration
Programmable service request nodes (SRNs)
Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per SRN to
choose from
Each SRN is mapped to the CPU interrupt system
– Up to 16 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
3-level programmable priority of the DMA Sub-Block at the on-chip bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered)
Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
– Continuous Mode: DMA channel remains enabled after a predefined number of
– Programmable address modification
– Two shadow register modes (with or without automatic re-set and direct write
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Data block move supports > 32 Kbyte per DMA transaction
– Circular buffer addressing mode with flexible circular buffer sizes
independent DMA channels
transfers
DMA transfers; DMA transaction can be repeated
access).
On-Chip System Units
Flexible Interrupt System
Direct Memory Access Controller
17
Introduction
V1.1, 2009-08
TC1736