SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 31

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Data Flash Features and Functions
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Data Sheet
Dynamic correction of single-bit errors during read access.
Transfer rate in burst mode: One 64-bit double-word per clock cycle.
Sector architecture:
– Eight 16 Kbyte, one 128 Kbyte and three 256 Kbyte sectors.
– Each sector separately erasable.
– Each sector lockable for protection against erase and program (write protection).
One additional configuration sector (not accessible to the user).
Optional read protection for whole Flash, with sophisticated read access supervision.
Combined with whole Flash write protection — thus supporting protection against
Trojan horse programs.
Sector specific write protection with support of re-programmability or locked forever.
Comfortable password checking for temporary disable of write or read protection.
User controlled configuration blocks (UCB) in configuration sector for keywords and
for sector-specific lock bits (one block for every user; up to three users).
Pad supply voltage (V
Efficient 256 byte page program operation.
All Flash operations controlled by CPU per command sequences (unlock sequences)
for protection against unintended operation.
End-of-busy as well as error reporting with interrupt and bus error trap.
Write state machine for automatic program and erase, including verification of
operation quality.
Support of margin check.
Delivery in erased state (read all zeros).
Global and sector status information.
Overlay support with SRAM for calibration applications.
Configurable wait state selection for different CPU frequencies.
Endurance = 1000; minimum 1000 program/erase cycles per physical sector;
reduced endurance of 100 per 16 KB sector.
Operating lifetime (incl. Retention): 20 years with endurance=1000.
For further operating conditions see data sheet section “Flash Memory Parameters”.
32 Kbyte on-chip Flash, configured in two independent Flash banks of equal size.
64 bit read interface.
Erase/program one bank while data read access from the other bank.
Programming one bank while erasing the other bank using an automatic
suspend/resume function.
Dynamic correction of single-bit errors during read access.
Sector architecture:
– Two sectors of equal size.
– Each sector separately erasable.
128 byte pages to be written in one step.
DDP
) also used for program and erase (no VPP pin).
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Introduction
V1.1, 2009-08
TC1736