UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 216

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UPSD3433E-40T6

Manufacturer Part Number
UPSD3433E-40T6
Description
MCU 8BIT 8032 128KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433E-40T6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4906

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PSD module
28.5.15
28.5.16
28.5.17
216/300
sequence is typically used when the 8032 is intentionally programming a large number of
bytes (such as during IAP). After intentional programming is complete, typically the Bypass
mode would be disabled, and full protection is back in place to prevent unwanted WRITEs to
Flash memory.
The Bypass Unlock mode is entered by first initiating two Unlock bus cycles. This is followed
by a third WRITE operation containing the Bypass Unlock command, 20h (as shown in
Table 163 on page
the Bypass Unlock mode. After this, a two bus cycle program operation is all that is required
to program a byte in this mode. The first bus cycle in this shortened program instruction
sequence contains the Bypassed Unlocked Program command, A0h, to any valid address
within the unlocked Flash array. The second bus cycle contains the address and data of the
byte to be programmed. Programming status is checked using toggle, polling, or
Ready/Busy just as before. Additional data bytes are programmed the same way until this
Bypass Unlock mode is exited.
To exit Bypass Unlock mode, the system must issue the Reset Bypass Unlock instruction
sequence. The first bus cycle of this instruction must write 90h to any valid address within
the unlocked Flash Array; the second bus cycle must write 00h to any valid address within
the unlocked Flash Array. After this sequence the Flash returns to Read Array mode.
During Bypass Unlock Mode, only the Bypassed Unlock Program instruction, or the Reset
Bypass Unlock instruction is valid, other instruction will be ignored.
Erasing Flash memory
Flash memory may be erased sector-by-sector, or an entire Flash memory array may be
erased with one command (bulk).
Flash bulk erase
The Flash Bulk Erase instruction sequence uses six WRITE operations followed by a READ
operation of the status register, as described in
Bulk Erase instruction sequence is wrong, the Bulk Erase instruction sequence aborts and
the device is reset to the Read Array mode. The address provided by the 8032 during the
Flash Bulk Erase command sequence may select any one of the eight Flash memory sector
select signals FSx or one of the four signals CSBOOTx. An erase of the entire Flash
memory array will occur in a particular array even though a command was sent to just one of
the individual Flash memory sectors within that array.
During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit
(DQ5), the Toggle Flag Bit (DQ6), and the Data Polling Flag Bit (DQ7). The Error Flag Bit
(DQ5) returns a ’1’ if there has been an erase failure. Details of acquiring the status of the
Bulk Erase operation are detailed in the section entitled
Flash memory on page
During a Bulk Erase operation, the Flash memory does not accept any other Flash
instruction sequences.
Flash sector erase
The Sector Erase instruction sequence uses six WRITE operations, as described in
Table 163 on page
same Flash array may be issued by the 8032 if the additional commands are sent within a
limited amount of time.
209. Additional Flash Sector Erase commands to other sectors within the
209). The Flash memory array that received that sequence then enters
212.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table 163 on page
“Section 28.5.10: Programming
209. If any byte of the

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