UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 253

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.55
28.5.56
Figure 89. Power-down mode flowchart
Chip select input (CSI)
Pin PD2 of Port D can optionally be configured in PSDsoft Express as the PSD module Chip
Select Input, CSI, which is an active-low logic input. By default, pin PD2 does not have the
CSI function.
When the CSI function is specified in PSDsoft Express, the CSI signal is automatically
included in DPLD chip select equations for FSx, CSBOOTx, RS0, and CSIOP. When the CSI
pin is driven to logic ’0’ from an external device, all of these memories will be available for
READ and WRITE operations. When CSI is driven to logic '1,' none of these memories are
available for selection, regardless of the address activity from the 8032, reducing power
consumption. The state of the PLD and port I/O pins are not changed when CSI goes to
logic ’1’ (disabled).
PLD non-turbo mode
The power consumption and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in the
csiop PMMR0 register. By setting this bit to logic '1,' the Turbo mode is turned off and both
PLDs consume only standby current when ALL PLD inputs have no transitions for an
extended time (65 ns for 5 V devices, 100 ns for 3.3 V devices), significantly reducing
current consumption. The PLDs will latch their outputs and go to standby, drawing very little
current. When Turbo mode is off, PLD propagation delay time is increased as shown in the
AC specifications for the PSD module. Since this additional propagation delay also effects
the DPLD, the response time of the memories on the PSD module is also lengthened by that
same amount of time. If Turbo mode is off, the user should add an additional wait state to the
8032 BUSCON SFR register if the 8032 clock frequency is higher that a particular value.
Please refer to
Table 51 on page 90
PLDs by setting PMMR0 bits 4 and 5,
OPTIONAL. Disable desired inputs to
and PMMR2 bits 2 through 6
NO
Module in Power-
in the MCU module section.
PDN = 1, PSD
for 15 CLKIN
Enable APD.
Set PMMR0,
Down Mode
YES
Bit 1 = 1
ALE idle
RESET
clocks?
AI09183
PSD module
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