UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 228

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

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Table 168. OMC port and data bit assignments (continued)
1. MCELLAB0-MCELLAB7 can be output to Port A pins only on 80-pin devices. Port A is not available on 52-
2. Port pins PC0, PC1, PC5, and PC6 are dedicated JTAG pins and are not available as outputs for
Loading and reading OMCs
Each of the two OMC groups (eight OMCs each) occupies a byte in csiop space, named
MCELLAB and MCELLBC (see
these two OMC registers in csiop it is accessing each of the OMCs through its 8-bit data
bus, with the bit assignment shown in
know the bit assignment when the user builds GPLD logic that is accessed by the 8032. For
example, the user may create a 4-bit counter that must be loaded and read by the 8032, so
the user must know which nibble in the corresponding csiop OMC register the firmware must
access. The fitter report generated by PSDsoft Express will indicate how it assigned the
OMCs and data bus bits to the logic. The user can optionally force PSDsoft Express to
assign logic to specific OMCs and data bus bits if desired by using the ‘PROPERTY’
statement in PSDsoft Express. Please see the PSDsoft Express User’s Manual for more
information on OMC assignments.
Loading the OMC flip-flops with data from the 8032 takes priority over the PLD logic
functions. As such, the preset, clear, and clock inputs to the flip-flop can be asynchronously
overridden when the 8032 writes to the csiop registers to load the individual OMCs.
Table 169. Output macrocell MCELLAB (address = csiop + offset 20h)
1. All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on
Table 170. Output macrocell MCELLBC (address = csiop + offset 21h)
1. All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on
MCELLAB
MCELLBC
MCELLBC3
MCELLBC4
MCELLBC5
MCELLBC6
MCELLBC7
pin devices.
MCELLBC 0, 1, 5, or 6.
reset).
reset).
Bit 7
Bit 7
OMC
7
7
MCELLAB
MCELLBC
Bit 6
Bit 6
assignment
6
6
Port B3 or C3
Port B4 or C4
Port B7 orC7
Port B5
Port B6
Port
MCELLAB
MCELLBC
Bit 5
Bit 5
(1),(2)
5
5
Table 169
terms from AND-OR
MCELLAB
MCELLBC
Native product
Bit 4
Bit 4
Table 168 on page
4
4
array
4
4
4
4
4
and
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Table
MCELLAB
MCELLBC
Bit 3
Bit 3
3
3
170). When the 8032 writes or reads
borrowed product
227. Sometimes it is important to
MCELLAB
MCELLBC
Maximum
terms
Bit 2
Bit 2
2
2
6
6
5
6
6
MCELLAB
MCELLBC
Bit 1
Bit 1
1
1
Data bit on 8032
(1)
(1)
reading OMC
data bus for
loading or
D3
D4
D5
D6
D7
MCELLAB
MCELLBC
Bit 0
Bit 0
0
0