UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 46

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

Special function registers (SFR)
Table 5.
46/300
(hex)
E0
addr
F0
SFR
DD
DE
EC
ED
DF
EA
EB
EE
EF
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
(1)
(1)
UBASEH
UBASEL
UADDR
S1ADR
S1STA
S1DAT
UPAIR
UCON
USIZE
USCV
name
UCTL
USEL
USTA
USCI
UIE0
UIE1
UIE2
UIE3
UIF0
UIF1
UIF2
UIF3
SFR
A
B
SFR memory map with direct address and reset value (continued)
BASEADDR[7:6]
GLF
DIR
GC
7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
<bit addresses: E7h, E6h, E5h, E4h, E3h, E2h, E1h, E0h>
<bit addresses: F7h, F6h, F5h, F4h, F3h, F2h, F1h, F0h>
STOP
INF
–
6
–
–
–
–
–
–
–
–
–
–
–
–
OUTF
INTR
Bit name and <bit address>
–
–
–
–
–
–
–
0
5
–
–
–
–
–
–
BASEADDR[15:8]
RESERVED
RESERVED
RESERVED
RESERVED
OUT4IE OUT3IE OUT2IE OUT1IE OUT0IE
NAK4IE NAK3IE NAK2IE NAK1IE NAK0IE
TX_MD B_BUSY B_LOST ACK_R
OUT4F
NAK4F
NAKF
S1ADR[7:0]
IN4IE
S1DAT[7:0]
IN4F
USCV[7:0]
4
–
–
–
–
–
–
0
–
USBADDR[6:0]
A[7:0]
B[7:0]
SIZE[6:0]
ENABLE STALL
PR3OU
OUT3F
NAK3F
RSTIE
UPSD3422, UPSD3433, UPSD3434, UPSD3454
RCVT
RSTF
IN3IE
IN3F
3
T
–
–
0
–
SUSPND
SUSPND
PR1OUT PR3IN PR1IN
USBEN
SETUP
OUT2F OUT1F OUT0F
NAK2F NAK1F NAK0F
IN2IE
IN2F
IE
F
2
0
USCI[2:0]
EP[2:0]
TOGGL
VISIBL
EOPIE
EOPF
IN1IE
IN1F
IN
E
E
1
0
RESUM
WAKEU
UMIE
IN0IE
IN0F
OUT
RES
BSY
SLV
P
0
F
0
Reset
value
(hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
08
00
00
00
00
00
Section 7.4
Section 7.5
with link
Table 78
Table 80
Table 82
descr.
Reg.