MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 134
MC68HC705C8ACP
Manufacturer Part Number
MC68HC705C8ACP
Description
IC MCU 4MHZ 8K OTP 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC68HC705C8ACFN.pdf
(222 pages)
Specifications of MC68HC705C8ACP
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
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Company:
Part Number:
MC68HC705C8ACP
Manufacturer:
MOTOROLA
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MC68HC705C8ACPE
Manufacturer:
ON
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Serial Communications Interface (SCI)
Technical Data
134
TDRE — Transmit Data Register Empty Bit
TC — Transmission Complete Bit
RDRF — Receive Data Register Full Bit
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
This clearable, read-only bit is set when the TDRE bit is set and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set and then reading the SCDR.
Reset clears the RDRF bit.
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in SCDR
0 = Received data not available in SCDR
1 = Receiver input idle
0 = Receiver input not idle
Serial Communications Interface (SCI)
Go to: www.freescale.com
MC68HC705C8A — Rev. 3
MOTOROLA
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