MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 102

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Hardware Multiply/Accumulate (MAC) Unit
3.1.3
The MAC unit supports the integer multiply operations defined by the baseline ColdFire architecture and
the new multiply-accumulate instructions.
3.1.4
The MAC unit supports three basic operand types:
3.2
For information on MAC instruction execution timings, refer to
3-4
Multiply Signed
Multiply Unsigned
Multiply Accumulate
Multiply Accumulate with
Load
Load Accumulator
Store Accumulator
Load MACSR
Store MACSR
Store MACSR to CCR
Load MASK
Store MASK
•
•
•
Instruction
Two’s complement signed integer: In this format, an N-bit operand represents a number within the
range -2
Two’s complement unsigned integer: In this format, an N-bit operand represents a number within
the range 0 < operand < 2
Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
bits signify the first N-1 bits after the binary point. Given an N-bit number, a
its value is given by the following formula:
This format can represent numbers in the range –1 < operand < 1 – 2
For words and longwords, the greatest negative number that can be represented is –1, whose
internal representation is 0x8000 and 0x0x8000_0000, respectively. The most positive word is
0x7FFF or (1 - 2
MAC Instruction
MAC Instruction Set Summary
Data Representation
(N-1)
< operand < 2
MCF5272 ColdFire
MULS <ea>y,Dx
MULU <ea>y,Dx
MAC Ry,RxSF
MSAC Ry,RxSF
MAC Ry,RxSF,Rw
MSAC Ry,RxSF,Rw
MOV.L {Ry,#imm},ACC
MOV.L ACC,Rx
MOV.L {Ry,#imm},MACSR
MOV.L MACSR,Rx
MOV.L MACSR,CCR
MOV.L {Ry,#imm},MASK
MOV.L MASK,Rx
-15
); the most positive longword is 0x7FFF_FFFF or (1 - 2
Mnemonic
N
Table 3-1. MAC Instruction Summary
Execution Timings
(N-1)
- 1. The binary point is to the right of the least significant bit.
®
- 1. The binary point is to the right of the least significant bit.
+
Integrated Microprocessor User’s Manual, Rev. 3
N 2
Table 3-1
i
∑
=
–
0
Multiplies two signed operands yielding a signed result
Multiplies two unsigned operands yielding an unsigned result
Multiplies two operands, then adds or subtracts the product to/from
the accumulator
Multiplies two operands, then adds or subtracts the product to/from
the accumulator while loading a register with the memory operand
Loads the accumulator with a 32-bit operand
Writes the contents of the accumulator to a register
Writes a value to the MACSR
Writes the contents of MACSR to a register
Writes the contents of MACSR to the processor’s CCR register
Writes a value to MASK
Writes the contents of MASK to a register
2
(
i
+
summarizes the MAC unit instruction set.
1 N
–
)
⋅
ai
Section 2.7, “Instruction
Description
(N-1)
.
-31
N-1
Freescale Semiconductor
).
a
N-2
Timing.”
a
N-3
... a
2
a
1
a
0
,