MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 116

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Local Memory
4.5.3.2
The ACRs define memory reference attributes for two memory regions (one per ACR). These attributes
affect every memory reference using the ACRs or the set of default attributes contained in the CACR.
ACRs are examined for each memory reference not mapped to the SRAM or ROM module. The
supervisor-level ACRs are accessed in the CPU address space using the MOVEC instruction with an Rc
encoding of 0x004 and 0x005. ACRs can be read and written in BDM mode.
Table 4-9
4-14
31–24
23–16
14–13
12–7
I
Bits
Bits
1–0
15
Reset
Field
R/W
Rc
Name
BAM
31
Name
EN
SM
CLNF
describes ACRn fields.
BA
—
Access Control Registers (ACR0 and ACR1)
Base address. Compared with A[31:24]. Eligible addresses that match are assigned the access control
attributes of this register.
Base address mask. Setting a BAM bit masks the corresponding BA bit. Setting low-order BAM bits can
define contiguous regions exceeding 16 Mbytes. BAM can define multiple noncontiguous regions.
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address range or if
the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
Reserved; should be cleared.
Control longword fetch. Controls the size of the memory request the cache issues to the bus controller for
different initial line access offsets.
BA
MCF5272 ColdFire
Figure 4-5. Access Control Register Format (ACRn)
24
Table 4-8. CACR Field Descriptions (continued)
CLNF
00
01
1x
23
Table 4-9. ACRn Field Descriptions
BAM
®
Integrated Microprocessor User’s Manual, Rev. 3
Line
Line
Line
00
Write (R/W by debug module)
ACR0: 0x004; ACR1: 0x005
16
0000_0000_0000_0000
Longword Address Bits
EN
15
Line
Line
Line
01
14
Description
Description
SM
Longword
13
Line
Line
10
12
Longword
Longword
—
Line
11
7
CM BWE
6
Freescale Semiconductor
5
4
—
3
WP —
2
1 0