MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 227

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

11.4.8
The FEC reports frame reception and transmission error conditions through the buffer descriptors and the
EIR register.
11.4.8.1
Transmission errors are defined in
1
11.4.8.2
Table 11-5
Freescale Semiconductor
Lost during Frame
Non-Octet Error
(Dribbling Bits)
Frame Length
Overrun Error
Retransmission
Late Collision
Attempts Limit
The definition of what constitutes a late collision is hard-wired in the FEC.
Carrier Sense
Transmission
CRC Error
Transmitter
Violation
Heartbeat
Underrun
Expired
Error
Error
describes reception errors.
Ethernet Error-Handling Procedure
1
Transmission Errors
Reception Errors
The FEC maintains an internal FIFO for receiving data. If a receiver FIFO overrun occurs, the FEC closes the
buffer and sets RxBD[OV].
The FEC handles up to seven dribbling bits when the receive frame terminates non-octet aligned and it checks
the CRC of the frame on the last octet boundary. If there is a CRC error, the frame non-octet aligned (NO)
error is reported in the RxBD. If there is no CRC error, no error is reported.
When a CRC error occurs with no dribbling bits, the FEC closes the buffer and sets RxBD[CR]. CRC checking
cannot be disabled, but the CRC error can be ignored if checking is not required.
When the receive frame length exceeds R_HASH[MAX_FRAME_LENGTH], EIR[BABR] is set indicating
babbling receive error, and the LG bit in the end of frame RxBD is set.
Note: Receive frames exceeding 2047 bytes are truncated.
The FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame
are then flushed and closed, with the UN bit set in the last TxBD for that frame. The FEC continues to the
next TxBD and begins transmitting the next frame.
When this error occurs and no collision is detected in the frame, the FEC sets the CSL bit in the last TxBD
for this frame. The frame is sent normally. No retries are performed as a result of this error. The CSL bit is
not set if TCR[FDEN] = 1, regardless of the state of CRS.
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are then
flushed and closed, with the RL bit set in the last TxBD for that frame. The FEC then continues to the next
TxBD and begins sending the next frame.
The FEC stops sending. All remaining buffers for that frame are then flushed and closed, with the LC bit set
in the last TxBD for that frame. The FEC then continues to the next TxBD and begins sending the next frame.
Some transceivers have a self-test feature called heartbeat or signal-quality error. To signify a good self-test,
the transceiver indicates a collision within 20 clocks after the FEC sends a frame. This heartbeat condition
does not imply a real collision, but that the transceiver seems to be functioning properly.
If TCR[HBC] is set and the heartbeat condition is not detected by the FEC after a frame transmission, then
a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets the HB bit in the Tx BD,
and generates the HBERR interrupt if it is enabled.
MCF5272 ColdFire
Table
Table 11-4. Transmission Errors
®
Table 11-5. Reception Errors
Integrated Microprocessor User’s Manual, Rev. 3
11-4.
Description
Description
Ethernet Module
11-9