MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 162

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
The following is a list of the key SIM features:
6.2
The following sections describe the registers incorporated into the SIM.
6.2.1
Table 6-1
memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This
supervisor-level register is described in
SIM registers depend on the base address defined in MBAR[BA], MBAR must be programmed before
SIM registers can be accessed.
6-2
•
•
•
•
•
•
•
Module base address register (MBAR)
— Base address location of all internal peripherals, SIM resources, and memory-mapped registers
— Address space masking to internal peripherals and SIM resources
Interrupt controller
— Programmable interrupt level (1–7) for internal peripheral interrupts
— Up to six external interrupt request inputs
— See
Chip select module
— Eight dedicated programmable chip selects
— Address masking for memory block sizes from 4 Kbytes to 2 Gbytes
— Programmable wait states and port sizes
— Programmable address setup
— Programmable address hold for read and write
— SDRAM controller interface supported with CS7/SDCS
See
System protection
— Hardware watchdog timer. See
— Software watchdog timer. See
Pin assignment register (PAR) configures the parallel port. See
Configuration Register
Power management
— Individual control for each on-chip peripheral
— Choice of low-power modes
See
Bus arbitration
— Configure arbitration for internal bus among ColdFire core, Ethernet controller, and DMA
Programming Model
shows the memory map for the SIM registers. The internal registers in the SIM are
controller. See
Chapter 8, “Chip Select
Section 6.2.5, “Power Management Register
SIM Register Memory Map
Chapter 7, “Interrupt
MCF5272 ColdFire
Section 6.2.3, “System Configuration Register
(SCR).”
Module.”
Controller.”
®
Section 6.2.2, “Module Base Address Register
Integrated Microprocessor User’s Manual, Rev. 3
Section 6.2.8, “Software Watchdog Timer
Section 6.2.3, “System Configuration Register
(PMR).”
Section 6.2.3, “System
(SCR).”
Freescale Semiconductor
(MBAR).” Because
(SCR).”