MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 352

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR].
This also causes QAR to increment. A read access requires a single wait state.
14.5.5
The QAR, shown in
operations affect.
14.5.6
The QDR, shown in
data from and to the QSPI RAM through this register. A read or write to QDR causes the value in QAR to
increment.
14-14
Address
Address
Reset
Reset
Field
Field
R/W
R/W
QSPI Address Register (QAR)
QSPI Data Register (QDR)
15
15
The QAR does not wrap after the last queue entry within each section of the
RAM.
Figure
Figure
MCF5272 ColdFire
14-10, is used to access QSPI RAM indirectly. The CPU reads and writes all
14-9, is used to specify the location in the QSPI RAM that read and write
Figure 14-9. QSPI Address Register
Figure 14-10. QSPI Data Register
®
Integrated Microprocessor User’s Manual, Rev. 3
—
0000_0000_0000_0000
0000_0000_0000_0000
NOTE
MBAR + 0x00B0
MBAR + 0x00B4
DATA
R/W
R/W
6
5
Freescale Semiconductor
ADDR
0
0