MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 293

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

request with the VEND_REQ interrupt. The user must take the following step to process a class or vendor
request:
12.4.6
The MCF5272 supports USB
remote wakeup capability. The three different resume mechanisms are listed below:
12.4.7
USB has the ability to halt endpoints due to errors. The user is notified when an endpoint is halted and
when the halt is cleared. When an endpoint is halted, the user should abort the current transfer and
reinitialize the FIFO for the endpoint. An endpoint can be halted for a variety of reasons.
A halted endpoint can be cleared in several different ways:
Freescale Semiconductor
1. Read DRR1 and DRR2 to determine the request type.
2. If the request has a data stage, the EP0 FIFO should be read or written with the number of bytes as
3. When the user has finished processing the request, EP0CTL[CMD_OVER] must be set to signal
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defined in the DRR2[wLength]. Refer to for more details on accessing the FIFOs.
completion of the request. [CMD_ERR] must also be set simultaneously if an error was
encountered while processing the request.
The user sets EP0CTL[RESUME]. The USB module responds to this only if the USB is in the
suspended state and EP0SR[WAKE_ST] is set. The ColdFire core must be running to write
E0PCTL. To meet USB timing specifications, the RESUME bit must not be set until two
milliseconds have elapsed since the USB module entered suspend state.
The wake-on-ring INT1 interrupt pin is at the active level defined in EP0CTL. The USB module
responds to the INT1 pin only if the wake-on-ring function is enabled, the USB is in the suspended
state and EP0SR[WAKE_ST] is set. The ColdFire core may be powered down, and the resume
signaling wakes up the ColdFire core. The wake-on-ring function must not be enabled until two
milliseconds have elapsed since the USB module entered the suspend state in order to meet USB
specification timing requirements.
The USB module detects any activity on the USB, which may be normal bus activity, resume
signaling, or reset signaling. The ColdFire core may be powered down, and the resume signaling
wakes up the ColdFire core.
SET
EPnCTL[STALL] is set by the user. This bit should be set only when there is a critical error on the
endpoint.
On control endpoints, an error processing a request.
CLEAR
A USB reset signal.
A
On control endpoints, a SETUP token for the next request.
SET
_
REMOTE WAKEUP
Endpoint Halt Feature
FEATURE
_
_
CONFIGURATION
FEATURE
request with the endpoint halt feature selector set.
MCF5272 ColdFire
request with the endpoint halt feature selector set.
RESUME
or
and
SET
_
®
initiated from three different sources. Two of the sources are for
INTERFACE
RESUME
Integrated Microprocessor User’s Manual, Rev. 3
Operation
request.
Universal Serial Bus (USB)
12-35