MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 77

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

2.2.2.3
The CACR controls operation of the instruction and data cache memory. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. See
2.2.2.4
The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions.
Attributes include definition of cache mode, write protect, and buffer write enables. See
“Access Control Registers (ACR0 and
2.2.2.5
The ROMBAR base address register determines the base address of the internal ROM module and
indicates the types of references mapped to it. The ROMBAR includes a base address, write-protect bit,
address space mask bits, and an enable. Note that the MCF5272 ROM contains data for the HDLC module
and is not user programmable. See
2.2.2.6
The RAMBAR register determines the base address location of the internal SRAM module and indicates
the types of references mapped to it. The RAMBAR includes a base address, write-protect bit, address
space mask bits, and an enable. The RAM base address must be aligned on a 0-modulo-4-Kbyte boundary.
See
2.2.2.7
The module base address register (MBAR) defines the logical base address for the memory-mapped space
containing the control registers for the on-chip peripherals. See
Register
2.3
Table 2-4
instructions. The operand size for each instruction is either explicitly encoded in the instruction or
implicitly defined by the instruction operation.
Freescale Semiconductor
Section 4.3.2.1, “SRAM Base Address Register
(MBAR).”
Integer Data Formats
lists the integer operand data formats. Integer operands can reside in registers, memory, or
Cache Control Register (CACR)
Access Control Registers (ACR0–ACR1)
ROM Base Address Register (ROMBAR)
RAM Base Address Register (RAMBAR)
Module Base Address Register (MBAR)
MCF5272 ColdFire
Section 4.5.3.1, “Cache Control Register
Bit
Byte integer
Word integer
Longword integer
Section 4.4.2.1, “ROM Base Address Register
Table 2-4. Integer Data Formats
®
Operand Data Format
ACR1).”
Integrated Microprocessor User’s Manual, Rev. 3
(RAMBAR).”
Section 6.2.2, “Module Base Address
16 bits
32 bits
8 bits
Size
1 bit
(CACR).”
(ROMBAR).”
Section 4.5.3.2,
ColdFire Core
2-9