UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet
UJA1078ATW/5V0/WD,
Specifications of UJA1078ATW/5V0/WD,
Related parts for UJA1078ATW/5V0/WD,
UJA1078ATW/5V0/WD, Summary of contents
Page 1
UJA1078A High-speed CAN/dual LIN core system basis chip Rev. 2 — 28 January 2011 1. General description The UJA1078A core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a high-speed Controller ...
Page 2
... NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and two LIN transceivers Scalable 3 voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB ...
Page 3
... NXP Semiconductors WAKE1 and WAKE2 inputs can be switched off to reduce current flow Output signal (WBIAS) to bias the wake-up pins, selectable sampling time Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller Sleep mode with very low sleep current and full wake-up capability 2 ...
Page 4
... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1078ATW/5V0/WD HTSSOP32 UJA1078ATW/3V3/WD UJA1078ATW/5V0 UJA1078ATW/3V3 [1] UJA1078ATW/5V0xx versions contain regulator (V1); UJA1078ATW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF ...
Page 5
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol TXDL2 RXDL2 TXDL1 V1 RXDL1 RSTN INTN EN SDI SDO SCK SCSN TXDC RXDC TEST1 WDOFF LIMP UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip TXDL2 1 RXDL2 2 3 TXDL1 ...
Page 6
... NXP Semiconductors Table 2. Symbol WAKE1 WAKE2 V2 CANH CANL GND SPLIT LIN1 DLIN LIN2 WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND ...
Page 7
... NXP Semiconductors 6.1 System Controller 6.1.1 Introduction The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The system controller is a state machine. The SBC operating modes, and how transitions between modes are triggered, are illustrated in more detail in the following sections ...
Page 8
... NXP Semiconductors V below BAT power-off threshold V th(det)poff (from all modes) V below BAT power-on threshold V th(det)pon CAN/LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1078A system controller UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip Overtemp V1: OFF V2: OFF limp home = LOW (active) ...
Page 9
... NXP Semiconductors 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (V and the bus systems are in a high-resistive state. The CAN bus pins are floating in this mode. As soon as the battery supply rises above the power-on detection threshold (V ...
Page 10
... NXP Semiconductors • The chip temperature rises above the OTP activation threshold, T SBC to switch to Overtemp mode 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register no pending interrupts (pin INTN = HIGH) or wake-up events and at least one wake-up source is enabled (CAN, LIN or WAKE) ...
Page 11
... NXP Semiconductors SCSN SCK 01 sampled SDI X SDO X floating Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. Address bits 15, 14 and 13 ...
Page 12
... NXP Semiconductors 6.2.3 WD_and_Status register Table 4. WD_and_Status register Bit Symbol Access Power-on default 15:13 A2, A1 000 WMC R/W 0 [1] 10:8 NWP R/W 100 7 WOS/SWR R V1S V2S WLS1 WLS2 R - 2:0 reserved R 000 [1] Bit NWP is set to its default value (100) after a reset. ...
Page 13
... NXP Semiconductors 6.2.4 Mode_Control register Table 5. Mode_Control register Bit Symbol Access Power-on default 15:13 A2, A1 001 12 RO R/W 0 11:10 MC R/W 00 [1] 9 LHWC R/W 1 [2] 8 LHC R ENC R LSC R WBC R PDC R/W 0 3:0 reserved R 0000 [1] Bit LHWC is set to 1 after a reset. [2] Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset. ...
Page 14
... NXP Semiconductors 6.2.5 Int_Control register Table 6. Int_Control register Bit Symbol Access Power-on default 15:13 A2, A1 010 V1UIE R V2UIE R STBCL1 R STBCL2 R/W 0 7:6 WIC1 R/W 00 5:4 WIC2 R/W 00 UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip Description register address ...
Page 15
... NXP Semiconductors Table 6. Int_Control register Bit Symbol Access Power-on default 3 STBCC R RTHC R WSE1 R WSE2 R/W 0 UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip …continued Description CAN standby control 0: When the SBC is in Normal mode (MC = 1x): CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared regardless of V2 output voltage ...
Page 16
... NXP Semiconductors 6.2.6 Int_Status register [1] Table 7. Int_Status register Bit Symbol Access Power-on default 15:13 A2, A1 011 V1UI R V2UI R LWI1 R LWI2 R R WI1 R POSI R WI2 R CWI R/W 0 2:0 reserved R 000 [1] An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register. ...
Page 17
... NXP Semiconductors 6.3 On-chip oscillator The on-chip oscillator provides the timing reference for the on-chip watchdog and the internal timers. The on-chip oscillator is supplied by an internal supply that is connected to V and is independent of V1/V2. BAT 6.4 Watchdog (UJA1078A/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms ...
Page 18
... NXP Semiconductors 6.4.2 Watchdog Timeout behavior The watchdog runs continuously in Timeout mode. It can be reset at any time by a watchdog trigger. If the watchdog overflows, the CI bit is set already pending, a system reset is performed. The watchdog is in Timeout mode when pin WDOFF is LOW and: • ...
Page 19
... NXP Semiconductors 6.5.1 RSTN pin A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t the microcontroller (external reset). A reset pulse is output on pin RSTN by the SBC when a system reset is triggered internally. The reset pulse width (t generated undervoltage event (see (V > V BAT selected by connecting a 900 Ω ...
Page 20
... NXP Semiconductors 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4 The SBC can handle maximum voltages the voltage on pin BAT falls below the power-off detection threshold (V SBC immediately enters Off mode, which means that the voltage regulators and the internal logic are shut down ...
Page 21
... NXP Semiconductors current current Fig 7. Figure 7 current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor its current limit. If the load current continues to rise, I increase above the selected PDC threshold (to a maximum of 250 mA). For a fast ramping load current, V1 will deliver the required load current (to a maximum of 250 mA) until the PNP transistor has switched on ...
Page 22
... The thermal performance of the transistor needs to be considered when calculating the value of this resistor. A 3.3 Ω resistor was used with the BCP52-16 (NXP Semiconductors) employed during testing. Note that the selection of the transistor is not critical. In general, any PNP transistor with a current amplification factor (β) of between 60 and 500 can be used ...
Page 23
... NXP Semiconductors 6.7.1 CAN operating modes 6.7.1.1 Active mode The CAN transceiver is in Active mode when: • the SBC is in Normal mode ( 11) • the transceiver is enabled (bit STBCC = 0; see and • enabled and its output voltage is above its undervoltage threshold • ...
Page 24
... NXP Semiconductors 6.7.2 Split circuit Pin SPLIT provides a DC stabilized voltage of 0.5V only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the center tap of the split termination (see A transceiver in the network that is not supplied and that generates a significant leakage current from the bus lines to ground, can result in a recessive bus voltage of < ...
Page 25
... NXP Semiconductors The transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN primarily intended for in-vehicle sub-networks using baud rates from 1 kBd kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant. UJA1078A BAT DLIN R1 master 1 kΩ ...
Page 26
... NXP Semiconductors 6.8.2 Fail-safe features 6.8.2.1 General fail-safe features The following fail-safe features have been implemented: • Pins TXDL1 and TXDL2 have internal pull-ups towards V states if these pins are left floating • The current of the transmitter output stage is limited in order to protect the transmitter against short circuits to pin BAT • ...
Page 27
... NXP Semiconductors The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are sampled continuously). The sampling will be performed on the rising edge of WBIAS (see Figure 13). The sampling time ms, is selected via the Wake Bias Control bit (WBC) in the Mode_Control register ...
Page 28
... NXP Semiconductors transmitters are switched off (see also temperature falls below the temperature shutdown threshold, the SBC will go to Standby mode. The temperature shutdown threshold is between 165 °C and 200 °C. UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip Section 6.1.6 “ ...
Page 29
... NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V voltage on pin reverse current from R(V1-BAT) pin V1 to pin BAT I current on pin DLIN DLIN V transient voltage trt V electrostatic ESD discharge voltage UJA1078A Product data sheet ...
Page 30
... NXP Semiconductors Table 8. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T virtual junction vj temperature T storage temperature stg T ambient amb temperature [1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from V1(+) to BAT (-). ...
Page 31
... NXP Semiconductors 8. Thermal characteristics Fig 15. HTSSOP PCB UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip PCB copper area: (bottom layer PCB copper area: (bottom layer measurements: board finish thickness 1.6 mm ±10 %, double-layer Layout conditions for R th(j-a) board, board dimensions 129 mm × 60 mm, board material FR4, Cu thickness 0.070 mm, thermal via separation 1.2 mm, thermal via diameter 0.3 mm ± ...
Page 32
... NXP Semiconductors R (K/W) Fig 16. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper Table 9. Symbol R th(j-a) [1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the first inner copper layer ...
Page 33
... NXP Semiconductors 9. Static characteristics Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter Supply; pin BAT V battery supply voltage BAT I battery supply current ...
Page 34
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter I additional battery supply BAT(add) current V power-on detection th(det)pon threshold voltage V power-off detection ...
Page 35
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter Voltage source; pin V1 V output voltage O R resistance between pin BAT (BAT-V1) ...
Page 36
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter I PNP deactivation threshold th(deact)PNP current PNP collector; pin VEXCC V current limiting activation ...
Page 37
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter I output leakage current LO Reset output with clamping detection; pin RSTN I HIGH-level output current ...
Page 38
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter CAN transmit data input; pin TXDC V switching threshold voltage th(sw) V input hysteresis voltage ...
Page 39
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter V differential receiver hys(RX)dif hysteresis voltage R common-mode input i(cm) resistance ΔR input resistance deviation ...
Page 40
... NXP Semiconductors Table 10. Static characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter I loss of battery leakage L(lob) current V receiver recessive voltage rec(RX) V receiver dominant voltage ...
Page 41
... NXP Semiconductors 10. Dynamic characteristics Table 11. Dynamic characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter Voltage source; pin V1 t undervoltage detection d(uvd) delay time t LOW-level clamping ...
Page 42
... NXP Semiconductors Table 11. Dynamic characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter t delay time from TXDC LOW d(TXDCL-RXDCL) to RXDC LOW t delay time from TXDC to ...
Page 43
... NXP Semiconductors Table 11. Dynamic characteristics − ° ° +150 4 BAT voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V otherwise specified. Symbol Parameter δ3 duty cycle 3 δ4 duty cycle 4 t rising receiver propagation PD(RX)r delay ...
Page 44
... NXP Semiconductors [5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t period (or in the first half of the watchdog period). [6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Window mode only. ...
Page 45
... NXP Semiconductors Fig 19. Timing test circuit for LIN transceivers V /V TXDL1 TXDL2 V BAT LIN1/LIN2 bus signal output of receiving V / RXDL1 node A V RXDL2 output of receiving V / RXDL1 node B V RXDL2 Fig 20. Timing diagram LIN transceivers UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip ...
Page 46
... NXP Semiconductors SCSN t SPILEAD SCK SDI X floating SDO Fig 21. SPI timing diagram 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. ...
Page 47
... NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 0.95 mm 1.1 0.25 ...
Page 48
... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 49
... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 50
... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip maximum peak temperature = MSL limit, damage level ...
Page 51
... NXP Semiconductors 14. Revision history Table 14. Revision history Document ID Release date UJA1078A v.2 20110128 • Modifications: Section • Figure • Table 8: parameter values/conditions revised - V • Table 9: parameter values/conditions revised - R • Table 10: parameter values/conditions revised - C • Table 11: parameter values/conditions revised - t UJA1078A v.1 20100709 ...
Page 52
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 53
... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: UJA1078A Product data sheet High-speed CAN/dual LIN core system basis chip 15 ...
Page 54
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 LIN transceivers . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 Control and diagnostic features . . . . . . . . . . . . 3 2.6 Voltage regulators Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description ...