UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet - Page 9

• Manufacturer Part Number: UJA1078ATW/5V0/WD,
• Description: IC SBC CAN/LIN 5.0V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/5V0/WD,

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1078A
Product data sheet
6.1.2 Off mode
6.1.3 Standby mode
6.1.4 Normal mode
The SBC switches to Off mode from all other modes if the battery supply drops below the
power-off detection threshold (V
and the bus systems are in a high-resistive state. The CAN bus pins are floating in this
mode.
As soon as the battery supply rises above the power-on detection threshold (V
the SBC goes to Standby mode, and a system reset is executed (reset pulse width of
t
The SBC will enter Standby mode:
In Standby mode, V1 is switched on. The CAN and LIN transceivers will either be in a
low-power state (Lowpower mode; STBCC/STBCL1/STBCL2 = 1; see
wake-up detection enabled or completely switched off (Off mode; STBCx = 0) - see
Section 6.7.1
mode, depending on the state of the WDOFF pin and the setting of the watchdog mode
control bit (WMC) in the WD_and_Status register
The SBC will exit Standby mode if:
Normal mode is selected from Standby mode by setting bits MC in the Mode_Control
register
In Normal mode, the CAN physical layer will be enabled (Active mode; STBCC = 0; see
Table
detection active.
In Normal mode, the LIN physical layers (LIN1 and LIN2) will be enabled (Active mode;
STBCL1/STBCL2 = 0; see
STBCL1/STBCL2 = 1) with bus wake-up detection active.
The SBC will exit Normal mode if:
w(rst)
•
•
•
•
•
•
•
•
•
•
From Off mode if V
From Sleep mode on the occurrence of a CAN, LIN or local wake-up event
From Overtemp mode if the chip temperature drops below the overtemperature
protection release threshold, T
From Normal mode if bit MC is set to 00 or a system reset is performed (see
Section
Normal mode is selected by setting bits MC to 10 (V2 disabled) or 11 (V2 enabled)
Sleep mode is selected by setting bits MC to 01
The chip temperature rises above the OverTemperature Protection (OTP) activation
threshold, T
Standby mode is selected by setting bits MC to 00
Sleep mode is selected by setting bits MC to 01
A system reset is generated (see
, long or short; see
6) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up
(Table
6.5)
and
5) to 10 (V2 disabled) or 11 (V2 enabled).
All information provided in this document is subject to legal disclaimers.
th(act)otp
Section
Rev. 2 — 28 January 2011
BAT
, causing the SBC to enter Overtemp mode
Section 6.5.1
6.8.1. The watchdog can be running in Timeout mode or Off
rises above the power-on detection threshold (V
Table
th(det)poff
6) or in a low-power state (Lowpower mode;
th(rel)otp
High-speed CAN/dual LIN core system basis chip
Section
and
). In Off mode, the voltage regulators are disabled
Table
6.1.3; the SBC will enter Standby mode)
11).
(Table
4).
UJA1078A
Table
© NXP B.V. 2011. All rights reserved.
th(det)on
6) with bus
th(det)on
)
9 of 54
),