UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet - Page 25

• Manufacturer Part Number: UJA1078ATW/5V0/WD,
• Description: IC SBC CAN/LIN 5.0V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/5V0/WD,

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1078A
Product data sheet
Fig 11. Typical master application
UJA1078A
6.8.1.1 Active mode
6.8.1.2 Lowpower/Off modes
6.8.1 LIN operating modes
DLIN
GND
LIN1
LIN2
BAT
The transceiver is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates
from 1 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
The LIN transceivers will be in Active mode when:
In LIN Active mode, the transceivers can transmit and receive data via the LIN bus pins.
The receiver detects data streams on the LIN bus pins (LIN1 and LIN2) and transfers
them to the microcontroller via pins RXDL1 and RXDL2 (see
represented by a HIGH level on RXDL1/RXDL2, LIN dominant by a LOW level.
The transmit data streams of the protocol controller at the TXDL inputs (TXDL1 and
TXDL2) are converted by the transmitter into bus signals with optimized slew rate and
wave shaping to minimize EME.
The LIN transceivers will be in Lowpower mode with bus wake-up detection enabled if bit
STBCLx = 1 (see
and LIN2 in Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceivers
will be in Off mode if bit STBCLx = 0. The LIN transceivers are powered down completely
in Off mode to minimize quiescent current consumption.
Filters at the receiver inputs prevent unwanted wake-up events due to automotive
transients or EMI. The wake-up event must remain valid for at least the minimum
dominant bus time for wake-up of the LIN transceivers, t
•
•
•
the SBC is in Normal mode (MC = 10 or 11) and
the transceivers are enabled (STBCL1 = 0 and/or STBCL2 = 0; see
the battery voltage (V
R1 master
1 kΩ
C1 master
All information provided in this document is subject to legal disclaimers.
R2 master
1 kΩ
C2 master
Table
Rev. 2 — 28 January 2011
015aaa228
to supply
LIN1 wire
LIN2 wire
6). The LIN transceivers can be woken up remotely via pins LIN1
BAT
) is above the LIN undervoltage recovery threshold, V
Fig 12. Typical slave application
High-speed CAN/dual LIN core system basis chip
UJA1078A
DLIN
GND
LIN1
BAT
wake(busdom)min
Figure
R1 slave
30 kΩ
C1 slave
UJA1078A
1) - LIN recessive is
(see
© NXP B.V. 2011. All rights reserved.
Table
Table
6) and
015aaa229
to supply
LIN1 wire
11).
uvr(LIN)
25 of 54
.