UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet - Page 17

• Manufacturer Part Number: UJA1078ATW/5V0/WD,
• Description: IC SBC CAN/LIN 5.0V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/5V0/WD,

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1078A
Product data sheet
6.4.1 Watchdog Window behavior
6.3 On-chip oscillator
6.4 Watchdog (UJA1078A/xx/WD versions)
The on-chip oscillator provides the timing reference for the on-chip watchdog and the
internal timers. The on-chip oscillator is supplied by an internal supply that is connected to
V
Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is
programmed via the NWP control bits in the WD_and_Status register (see
default watchdog period is 128 ms.
A watchdog trigger event is any write access to the WD_and_Status register. When the
watchdog is triggered, the watchdog timer is reset.
In watchdog Window mode, a watchdog trigger event within a closed watchdog window
(i.e. the first half of the window before t
is triggered before the watchdog timer overflows in Timeout or Window mode, or within
the open watchdog window (after t
immediately.
The following watchdog events result in an immediate system reset:
After a watchdog reset (short reset; see
period is selected (NWP = 100). The watchdog can be switched off completely by forcing
pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in
Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will
re-enable it.
Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is
pending. Any attempt to change WMC when an interrupt is pending will be ignored.
The watchdog runs continuously in Window mode.
If the watchdog overflows, or is triggered in the first half of the watchdog period (less than
t
Watchdog overflow occurs if the watchdog is not triggered within t
the watchdog period.
If the watchdog is triggered in the second half of the watchdog period (at least t
not more than t
The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode
and the watchdog mode control bit (WMC) is set to 0.
trig(wd)1
BAT
•
•
•
•
•
the watchdog overflows in Window mode
the watchdog is triggered in the first half of the watchdog period in Window mode
the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending
the state of the WDOFF pin changes in Normal mode or Standby mode
the watchdog mode control bit (WMC) changes state in Normal mode
and is independent of V1/V2.
after the start of the watchdog period), a system reset will be performed.
trig(wd)2
All information provided in this document is subject to legal disclaimers.
, after the start of the watchdog period), the watchdog will be reset.
Rev. 2 — 28 January 2011
trig(wd)1
High-speed CAN/dual LIN core system basis chip
trig(wd)1
Section 6.5.1
but before t
) will generate an SBC reset. If the watchdog
trig(wd)2
and
Table
), the timer restarts
11), the default watchdog
trig(wd)2
UJA1078A
© NXP B.V. 2011. All rights reserved.
after the start of
Table
trig(wd)1
4). The
17 of 54
, but