UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet - Page 41

• Manufacturer Part Number: UJA1078ATW/5V0/WD,
• Description: IC SBC CAN/LIN 5.0V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/5V0/WD,

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
10. Dynamic characteristics
Table 11.
T
voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V
otherwise specified.
UJA1078A
Product data sheet
Symbol
Voltage source; pin V1
t
t
Voltage source; pin V2
t
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
t
t
t
t
t
t
t
t
Reset output; pin RSTN
t
t
t
Watchdog off input; pin WDOFF
t
Wake input; pin WAKE1, WAKE2
t
t
CAN transceiver timing; pins CANH, CANL, TXDC and RXDC
t
d(uvd)
det(CL)L
d(uvd)
cy(clk)
SPILEAD
SPILAG
clk(H)
clk(L)
su(D)
h(D)
v(Q)
WH(S)
w(rst)
det(CL)L
fltr
fltr
wake
d(po)
d(TXDCH-RXDCH)
vj
=
−
40
°
C to +150
Dynamic characteristics
Parameter
undervoltage detection
delay time
LOW-level clamping
detection time
undervoltage detection
delay time
clock cycle time
SPI enable lead time
SPI enable lag time
clock HIGH time
clock LOW time
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH V
reset pulse width
LOW-level clamping
detection time
filter time
filter time
wake-up time
power-on delay time
delay time from TXDC HIGH
to RXDC HIGH
°
C; V
BAT
= 4.5 V to 28 V; V
All information provided in this document is subject to legal disclaimers.
BAT
V
V
V
V
V
V
pin SDO; V
Conditions
V
V
V
V
when SPI select falls
when SPI select rises
V
C
long; R
short; R
RSTN driven HIGH internally but pin
RSTN remains LOW; V
(WD versions only)
50 % V
V
R
C
f
TXDC
V1
V1
WDOFF
V2
V1
V1
V1
V1
V1
V1
V1
V1
V2
L
(CANH-CANL)
(CANH-CANL)
Rev. 2 — 28 January 2011
> V
= 100 pF
falling; dV
< 0.9V
falling, dV
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 4.5 V to 5.5 V
= 250 kHz
V1
pu(RSTN)
TXDC
pu(RSTN)
; V
= 0 V (WD versions only)
O(V1)nom
BAT
V1
to 50 % V
= 60 Ω
= 100 pF; C
= 2.97 V to 5.5 V
V1
V2
> V
> 25 kΩ
/dt = 0.1 V/μs
/dt = 0.1 V/us
= 900 Ω to 1100 Ω
High-speed CAN/dual LIN core system basis chip
V2
; V1 active
; R
RXDC
LIN1
WDOFF
RXDC
= R
= 0 V
= 15 pF
LIN2
= 500
Ω
; R
160
7
10
113
Min
7
95
7
320
110
140
160
0
80
-
20
20
3.6
95
0.9
60
(CANH-CANL)
UJA1078A
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BAT
© NXP B.V. 2011. All rights reserved.
= 45
= 14 V; unless
140
-
-
25
5
140
18
40
278
Max
23
23
-
-
-
-
-
110
-
2.3
235
Ω
to 65
41 of 54
Ω
Unit
μs
ms
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
μs
ms
μs
μs
ns
; all