UJA1078ATW/5V0/WD, NXP Semiconductors, UJA1078ATW/5V0/WD, Datasheet - Page 14

• Manufacturer Part Number: UJA1078ATW/5V0/WD,
• Description: IC SBC CAN/LIN 5.0V HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1078ATW/5V0/WD,

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 84µA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 6.
UJA1078A
Product data sheet
Bit
15:13
12
11
10
9
8
7:6
5:4
Symbol
A2, A1, A0 R
RO
V1UIE
V2UIE
STBCL1
STBCL2
WIC1
WIC2
Int_Control register
6.2.5 Int_Control register
Access Power-on
R/W
R/W
R/W
R/W
R/W
R/W
R/W
default
010
0
0
0
0
0
00
00
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
V1 undervoltage interrupt enable
V2 undervoltage interrupt enable
LIN1 standby control
LIN2 standby control
wake-up interrupt 1 control
wake-up interrupt 2 control
0: register set to read/write
1: register set to read only
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
0: When the SBC is in Normal mode (MC = 1x):
1: LIN1 is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). LIN1 wake-up interrupts can be
requested.
0: When the SBC is in Normal mode (MC = 1x):
1: LIN2 is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). LIN2 wake-up interrupts can be
requested.
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
When the SBC is in Standby/Sleep mode (MC = 0x):
When the SBC is in Standby/Sleep mode (MC = 0x):
LIN1 is in Active mode. The wake-up flag (visible on RXDL1) is cleared
regardless of the value of V
LIN1 is in Off mode. Bus wake-up detection is disabled. LIN1 wake-up
interrupts cannot be requested.
LIN2 is in Active mode. The wake-up flag (visible on RXDL2) is cleared
regardless of the value of V
LIN2 is in Off mode. Bus wake-up detection is disabled. LIN2 wake-up
interrupts cannot be requested.
Rev. 2 — 28 January 2011
High-speed CAN/dual LIN core system basis chip
BAT
BAT
.
.
UJA1078A
© NXP B.V. 2011. All rights reserved.
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