UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 186
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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Address: FFB6H
Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01).
Symbol
TMC01
OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match
between TM01 and CR001).
It can also be set to 1 by writing 1 to OVF01.
Clear (0)
TMC013
TMC011
OVF01
Set (1)
0
0
1
1
0
1
7
0
After reset: 00H
Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01)
• Match between TM01 and CR001 or match between TM01 and CR011
• Match between TM01 and CR001 or match between TM01 and CR011
• Trigger input of TI001 pin valid edge
Clears OVF01 to 0 or TMC013 and TMC012 = 00
Overflow occurs.
TMC012
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
0
1
0
1
6
0
R/W
Disables 16-bit timer/event counter 01 operation. Stops supplying operating clock.
Clears 16-bit timer counter 01 (TM01).
Free-running timer mode
Clear & start mode entered by TI001 pin valid edge input
Clear & start mode entered upon a match between TM01 and CR001
5
0
User’s Manual U17260EJ6V0UD
Condition to reverse timer output (TO01)
Operation enable of 16-bit timer/event counter 01
4
0
TM01 overflow flag
TMC013
3
TMC012
2
Note
TMC011
1
OVF01
<0>
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