UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 422

• Manufacturer Part Number: UPD78F0535GB(T)-UEU-A
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0535GB(T)-UEU-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 60KB
• Oscillator Type: External, Internal

422
Address: FFA6H
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• Reset
WREL0
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
Caution The start condition is detected immediately after I
LREL0
Symbol
IICC0
IICE0
0
1
0
1
0
1
Note 2
Note 2
2. This flag’s signal is invalid when IICE0 = 0.
IICCL0 register are reset.
SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I
operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0
after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
Stop operation. Reset IIC status register 0 (IICS0)
Enable operation.
IICE0
<7>
After reset: 00H
LREL0
<6>
Figure 17-5. Format of IIC Control Register 0 (IICC0) (1/4)
WREL0
<5>
R/W
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
SPIE0
<4>
Exit from communications
I
2
C operation enable
Wait cancellation
WTIM0
Note 1
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Condition for setting (WREL0 = 1)
• Set by instruction
<3>
. Stop internal operation.
2
C is enabled to operate (IICE0 = 1) while the
ACKE0
<2>
STT0
<1>
SPT0
<0>
2
C to