UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 747

• Manufacturer Part Number: UPD78F0535GB(T)-UEU-A
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0535GB(T)-UEU-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 60KB
• Oscillator Type: External, Internal

Standby
function
Function
OSTS:
Oscillation
stabilization time
select register
STOP mode
Details of
Function
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to
the HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
Even if “internal low-speed oscillator can be stopped by software” is selected by the
option byte, the internal low-speed oscillation clock continues in the STOP mode in
the status before the STOP mode is set. To stop the internal low-speed oscillator’s
oscillation in the STOP mode, stop it by software and then execute the STOP
instruction.
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the next execution
of the STOP instruction. Before changing the CPU clock from the internal high-
speed oscillation clock to the high-speed system clock (X1 oscillation) after the
STOP mode is released, check the oscillation stabilization time with the oscillation
stabilization time counter status register (OSTC).
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12
high-speed oscillation clock is selected as the CPU clock, or for the duration of 160
external clocks when the high-speed system clock (external clock input) is selected
as the CPU clock.
OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
µ
s after the STOP mode is released when the internal
Cautions
p. 519
p. 519
p. 519
p. 519
p. 525
p. 527
p. 527
p. 527
p. 527
(21/25)
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