UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 254

• Manufacturer Part Number: UPD78F0535GB(T)-UEU-A
• Description: 8BIT MCU, 60K FLASH, 3KB RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0535GB(T)-UEU-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 60KB
• Oscillator Type: External, Internal

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8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
(1) Timer clock selection register 5n (TCL5n)
254
The following four registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 1 (PM1) or port mode register 3 (PM3)
• Port register 1 (P1) or port register 3 (P3)
Notes 1.
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
Remark f
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TCL5n to 00H.
Remark n = 0, 1
Address: FF6AH
Symbol
TCL50
2.
2. Be sure to clear bits 3 to 7 to “0”.
PRS
If the peripheral hardware clock (f
f
• V
• V
• V
If the peripheral hardware clock (f
= 0), when 1.8 V ≤ V
prohibited.
PRS
: Peripheral hardware clock frequency
DD
DD
DD
TCL502
operating frequency varies depending on the supply voltage.
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
7
0
0
0
0
0
1
1
1
1
After reset: 00H
Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
TCL501
6
0
0
0
1
1
0
0
1
1
DD
PRS
PRS
PRS
< 2.7 V, the setting of TCL502, TCL501, TCL500 = 0, 1, 0 (count clock: f
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
R/W
TCL500
User’s Manual U17260EJ6V0UD
5
0
0
1
0
1
0
1
0
1
PRS
PRS
) operates on the internal high-speed oscillation clock (f
) operates on the high-speed system clock (f
TI50 pin falling edge
TI50 pin rising edge
f
f
f
f
f
f
PRS
PRS
PRS
PRS
PRS
PRS
Note 2
/2
/2
/2
/2
/2
4
0
2
6
8
13
2 MHz
1 MHz
500 kHz
31.25 kHz
7.81 kHz
0.24 kHz
2 MHz
f
PRS
3
0
Count clock selection
=
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
19.53 kHz
0.61 kHz
TCL502
5 MHz
f
PRS
2
=
10 MHz
5 MHz
2.5 MHz
156.25 kHz 312.5 kHz
39.06 kHz
1.22 kHz
Note 1
TCL501
10 MHz
f
PRS
1
=
XH
) (XSEL = 1), the
20 MHz
10 MHz
5 MHz
78.13 kHz
2.44 kHz
TCL500
20 MHz
f
PRS
0
RH
=
) (XSEL
PRS
) is