UPD78F0535GB(T)-UEU-A NEC, UPD78F0535GB(T)-UEU-A Datasheet - Page 534
UPD78F0535GB(T)-UEU-A
Manufacturer Part Number
UPD78F0535GB(T)-UEU-A
Description
8BIT MCU, 60K FLASH, 3KB RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0535GB(T)-UEU-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
60KB
Oscillator Type
External, Internal
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(when X1 oscillation is selected)
Note Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
High-speed system clock
Internal reset signal
Internal high-speed
oscillation clock
(except P130)
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 23
CPU clock
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
POWER-ON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR.
RESET
Port pin
Port pin
(P130)
Figure 22-4. Timing of Reset in STOP Mode by RESET Input
operation
Normal
STOP instruction execution
CHAPTER 22 RESET FUNCTION
(oscillation stop)
Stop status
User’s Manual U17260EJ6V0UD
Delay
(oscillation stop)
Reset period
(5 s (TYP.))
µ
Delay
accuracy stabilization
Wait for oscillation
(86 to 361 s)
(11 to 45 s)
processing
Reset
µ
µ
Hi-Z
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Note
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