EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 195

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

Mode
Shift
0x0
0x0
0x1
0x1
0x2
0x3
0x4
0x5
0x0
0x1
Color
Mode
0x0
0x4
0x8
0x5
0x6
0x0
0x4
0x8
0x5
0x6
0x0
0x8
0x0
0x8
0x0
0x8
0x0
0x8
pixel mapped
565 pixel per
555 pixel per
per clock up
single 16-bit
single 16-bit
single 24-bit
single 16-bit
18 bits each
single 16-bit
18 bits each
progressive
progressive
progressive
single pixel
2 pixels per
4 pixels per
8 pixels per
2 2/3 pixels
mapped to
mapped to
shift clock
dual scan
shift clock
dual scan
shift clock
dual scan
to 24 bits
to 18 bits
565 pixel
555 pixel
per clock
Output
each clk
Mode
clock
clock
scan
scan
scan
wide
clk
clk
P1(20)
P3(14)
P1(14)
P7(23)
P3(23)
P(23) P(22) P(21) P(20) P(19) P(18) P(17) P(16) P(15) P(14) P(13) P(12) P(11) P(10) P(9) P(8) P(7) P(6) P(5) P(4) P(3) P(2) P(1) P(0)
Lower
G3(6)
Lower
G1(6)
Lower
R1(4)
P(20)
R(1)
R(3)
R(3)
R(4)
R7
R3
X
X
X
X
X
X
*
*
*
*
*
*
P1(12)
P6(23)
P3(23)
Lower
Lower
Upper
G1(4)
P(12)
P3(6)
B3(6)
P1(6)
B1(6)
R(0)
R(2)
R(2)
G(4)
R6
R3
X
X
X
X
X
X
*
*
*
*
*
*
P2(14)
P1(14)
P5(23)
P2(23)
Lower
Upper
Lower
P1(4)
B1(4)
B2(6)
G1(6)
G(1)
G(5)
G(3)
P(4)
B(4)
R5
R2
X
X
X
X
X
X
*
*
*
*
*
*
P0(20)
P4(23)
P2(23)
Upper
Upper
Upper
R0(4)
P(20)
P2(6)
B2(6)
P1(6)
B1(6)
G(0)
G(4)
G(2)
R(4)
R4
R2
X
X
X
X
X
X
*
*
*
*
*
*
P0(12)
P1(14)
P0(14)
P3(23)
P1(23)
Upper
Lower
Lower
G0(4)
P(12)
G1(6)
G0(6)
B(1)
B(3)
B(3)
G(4)
R3
R1
X
X
X
X
X
X
*
*
*
*
*
*
P2(23)
P1(23)
Upper
Lower
Upper
P0(4)
B0(4)
P1(6)
B1(6)
P0(6)
B0(6)
B(0)
B(2)
P(2)
P(4)
B(4)
R2
R1
X
X
X
X
X
X
*
*
*
*
*
*
P1(23)
P0(14)
P0(14)
P1(23)
P0(23)
Lower
Upper
Lower
R1(7)
P(23)
G0(6)
G0(6)
Table 7-3. Output Pixel Transfer Modes
R(7)
R(4)
R(4)
R(7)
R(4)
R(4)
R(7)
R1
R0
X
X
X
*
*
*
*
P1(22)
P0(23)
P0(23)
Lower
Upper
Upper
G1(6)
P(22)
P0(6)
B0(6)
P0(6)
B0(6)
R(6)
R(3)
R(3)
R(6)
R(3)
R(3)
R(6)
R0
R0
X
X
X
*
*
*
*
P1(21)
P3(23)
P1(23)
P7(15)
P3(15)
G1(5)
Lower
Lower
Lower
P(21)
R3(7)
R1(7)
R(5)
R(2)
R(2)
R(5)
R(2)
R(2)
R(5)
G7
G3
X
X
X
*
*
P1(15)
P3(22)
P1(22)
Lower
Lower
Lower
G1(7)
P(15)
R3(6)
R1(6)
P7(7)
P3(7)
R(4)
R(1)
R(1)
R(4)
R(1)
R(1)
G(7)
B7
B3
X
X
X
*
*
*
*
P1(14)
P3(15)
P1(15)
P6(15)
P3(15)
G1(6)
Lower
G3(7)
Lower
G1(7)
Upper
P(14)
R(3)
R(0)
R(0)
R(3)
R(0)
R(0)
G(6)
G6
G3
X
X
X
*
*
P1(13)
Lower
Lower
Upper
G1(5)
P(13)
P3(7)
B3(7)
P1(7)
B1(7)
P6(7)
P3(7)
G(5)
R(2)
R(4)
R(4)
R(2)
R(4)
R(4)
B6
B3
X
X
X
*
*
*
*
*
P2(23)
P1(23)
P5(15)
P2(15)
Lower
Upper
Lower
P1(7)
B1(7)
R2(7)
R1(7)
G(7)
G(5)
G(4)
G(7)
G(5)
G(4)
P(7)
B(7)
G5
G2
X
X
X
*
*
P2(22)
P1(22)
Lower
Upper
Lower
R2(6)
R1(6)
P1(6)
B1(6)
P5(7)
P2(7)
G(6)
G(4)
G(3)
G(6)
G(4)
G(3)
P(6)
B(6)
B5
B2
X
X
X
*
*
*
*
P2(15)
P1(15)
P4(15)
P2(15)
Lower
Upper
Upper
P1(5)
B1(5)
G2(7)
G1(7)
G(5)
G(3)
G(2)
G(5)
G(3)
G(2)
P(5)
B(5)
G4
G2
X
X
X
*
*
P0(23)
Upper
Upper
Upper
R0(7)
P(23)
P2(7)
B2(7)
P1(7)
B1(7)
P4(7)
P2(7)
G(4)
G(2)
G(1)
G(4)
G(2)
G(1)
R(7)
B4
B2
X
X
X
*
*
P0(22)
P1(23)
P0(23)
P3(15)
P1(15)
R0(6)
Upper
R1(7)
Lower
R0(7)
Lower
P(22)
G(3)
G(1)
G(0)
G(3)
G(1)
G(0)
R(6)
G3
G1
G2
B5
R7
*
*
P0(21)
P1(22)
P0(22)
Upper
Lower
Lower
R0(5)
P(21)
R1(6)
R0(6)
P3(7)
P1(7)
G(2)
G(0)
G(4)
G(2)
G(0)
G(4)
R(5)
B3
B1
B2
R4
G7
*
*
*
*
*
*
*
P0(15)
P1(15)
P0(15)
P2(15)
P1(15)
Upper
Lower
Upper
G0(7)
G1(7)
G0(7)
P(15)
B(7)
B(4)
B(4)
B(7)
B(4)
B(4)
G(7)
G2
G1
R1
G4
B7
*
*
P0(14)
Upper
Lower
Upper
G0(6)
P(14)
P1(7)
B1(7)
P0(7)
B0(7)
P2(7)
P1(7)
G(6)
B(6)
B(3)
B(3)
B(6)
B(3)
B(3)
G1
R6
B2
B1
B4
*
*
P0(13)
P0(23)
P0(23)
P1(15)
P0(15)
Upper
Upper
Lower
G0(5)
P(13)
R0(7)
R0(7)
G(5)
B(5)
B(2)
B(2)
B(5)
B(2)
B(2)
G1
G0
R3
G6
B1
*
*
P0(22)
P0(22)
Upper
R0(6)
Upper
R0(6)
Lower
P0(7)
B0(7)
P1(7)
P0(7)
B(4)
B(1)
B(1)
B(4)
B(1)
B(1)
P(7)
B(7)
G3
B1
B0
R0
B6
*
*
*
*
P0(15)
P0(15)
P0(15)
P0(15)
Upper
G0(7)
Upper
G0(7)
Upper
P0(6)
B0(6)
B(3)
B(0)
B(0)
B(3)
B(0)
B(0)
P(6)
B(6)
G0
G0
G0
B3
R5
*
*
Upper
Upper
Upper
P0(5)
B0(5)
P0(7)
B0(7)
P0(7)
B0(7)
P0(7)
P0(7)
B(2)
B(4)
B(4)
B(2)
B(4)
B(4)
P(5)
B(5)
77
B0
B0
B0
R2
G5
*
*
*
*
*