EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 434

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

10
10-40
DMA Controller
EP93xx User’s Guide
DREQS:
Copyright 2007 Cirrus Logic
The NextBuffer status bit can be used in conjunction with
the CurrentState status bits to determine the active buffer
according to the following rules:
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 1
then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_ON and NextBuffer = 0
then Buffer1 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =
0 then Buffer0 is the active buffer.
If CurrentState[4:3] = DMA_BUF_NEXT and NextBuffer =1
then Buffer1 is the active buffer.
DREQ Status - This bit reflects the status of the
synchronized external DMA Request signal or IDE/SSP
requests:
0 - No external DMA request is pending or, in the case of a
transfer without handshaking, the request is not validated
yet, the wait state counter is running.
1 - An external DMA request or a validated IDE/SSP or
external peripheral without handshaking request is
pending.
DREQS can be polled by software at any time. It can, for
example, be used to determine whether or not the DMA
needs to be set up for a transfer when the DMA is in the
STALL state and is receiving DREQs, but the BCRx
registers have not been programmed. It is important to
notice that, in the case of a transfer without handshaking
(external DMA or IDE or SSP), DREQS might be clear if a
request is pending but is not validated as a result of a wait
state counter still running.
When the channel STATUS register is written with any 32-
bit value, this will cause the DREQS bit of the STATUS
register to be cleared. A write to the STATUS register only
affects the DREQS bit. If an edge is detected on DREQ
when no previous request is still pending in the DMA (that
is, DREQS clear), then the DREQS bit is set by the DMA
DS785UM1