EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 358

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

9
RXRuntCnt
9-56
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Receive Miss Count Register
RSVD:
RMC:
0x8001_0078 - Read Only
0x0000_0000
0x0000_0000
Receive Runt Count Register
RSVD:
RRC:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Miss Count. The Receive Miss Count records the
number of frames that pass the destination address filter,
but fail to be received due to lack of bus availability or lack
of receive storage. Frames that are partially stored and
marked as overruns are included in the count. When the
most significant bit of the count is set, an optional interrupt
may be generated. The register is cleared automatically
following a read, writing to the register will have no effect.
Reserved. Unknown During Read.
Receive Runt Count. The receive runt count records the
total number of runt frames received, including those with
bad CRC. When the most significant bit of the count is set,
an optional interrupt may be generated. The register is
cleared automatically following a read, writing to the
register will have no effect.
24
8
RSVD
RRC
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0