EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 721

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
23.5.10 Motorola SPI Format with SPO=1, SPH=1
SFRMOUT /
SCLKOUT /
SCLKIN
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW, which causes
slave data to be immediately transferred onto the SSPRXD line of the master. The master
SSPTXD output pad is enabled.
One half period later, valid master data is transferred to the SSPTXD line. Now that both the
master and slave data have been set, the SCLKOUT master clock pin becomes LOW after
one further half SCLKOUT period. This means that data is captured on the falling edges and
is propagated on the rising edges of the SCLKOUT signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SFRMOUT line is returned to its idle HIGH state one SCLKOUT period after the last bit has
been captured.
However, in the case of continuous back-to-back transmissions, the SFRMOUT signal must
be pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the SPH
bit is logic zero. Therefore the master device must raise the SFRMIN pin of the slave device
between each data transfer to enable the serial peripheral data write. On completion of the
continuous transfer, the SFRMOUT pin is returned to its idle state one SCLKOUT period after
the last bit has been captured.
The transfer signal sequence for Motorola SPI format with SPO=1, SPH=1 is shown in
Figure
In this configuration, during idle periods:
SFRMIN
SSPRXD
Note:
SSPTXD
• the SCLKOUT signal is forced HIGH
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
SSPOE
23-8, which covers both single and continuous transfers.
Figure
23-8, Q is an undefined signal.
Q
Figure 23-8. Motorola SPI Frame Format with SPO=1 and SPH=1
M SB
MS B
Copyright 2007 Cirrus Logic
4 t o 16 bi t s
Synchronous Serial Port
EP93xx User’s Guide
LS B
LS B
Q
23-9
23