EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 779

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
27.2.7.3.3 Ultra DMA Read from IDE Controller
27.2.7.3.4 Ultra DMA Write to IDE Controller
27.2.8 IDE Package Dependency
27.2.8.1 System Configuration Constraints
27.2.8.2 Bus Bandwidth Requirements
Follow the wait-state number listed in the wait-state table in
However, the DMA request will not assert unless there are 4 words present in the read FIFO
or the transfer is non-quad aligned and has the last remaining bits of data, so quad-word
bursts are permissible if the total Ultra DMA transfer size is quad-word aligned.
Although the DMA request line has a non-insignificant DMAIDE latency, the DMA write FIFO
is of sufficient size to absorb any overage incurred during the DMA request latency period.
The DMA controller can be run without wait-states. Quad-word bursts are permissible if the
Ultra DMA transfer size is quad-word aligned.
The block uses the following external pins:
IDECS0n, IDECS1n, IDEDA, DIORn, DIOWn, DMACKn, DD, IORDY, INT[3], EGPIO[2],
and EGPIO[15].
The following system configuration modes force the disabling of the IDE controller:
The block does not have any hard bandwidth constraints because it can throttle performance
to the available bandwidth without data corruption. The maximum free bandwidth that the
block will consume is limited by the IDE mode the device is in. Maximum theoretical
bandwidths are listed in
- GPIOEonIDE
- GPIOFonIDE
- GPIOGonIDE
- GPIOHonIDE
Table 27-5. Maximum Theoretical Bandwidths for Various Operating Modes
MDMA Mode 0
MDMA Mode 1
MDMA Mode 2
PIO Mode 0
PIO Mode 1
PIO Mode 2
PIO Mode 3
PIO Mode 4
Mode
Table
Copyright 2007 Cirrus Logic
27-5.
MAX IDE Device Bandwidth
16.67 MBps
13.33 MBps
16.67 MBps
11.11 MBps
3.33 MBps
5.22 MBps
8.33 MBps
4.17 MBps
Table 27-3
and
EP93xx User’s Guide
Table
IDE Interface
27-4.
27-9
27