EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 63

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
0x800C_022C
0x800C_0230
0x800C_0234
0x800C_0238
0x800C_023C
0x800C_0FE0
0x800C_0FE4
0x800C_0FE8
0x800C_0FEC
0x800C_0FF0 - 0x800C_0FFC
0x8081_xxxx
0x8081_0000
0x8081_0004
0x8081_0008
0x8081_000C
0x8081_0020
0x8081_0024
0x8081_0028
0x8081_002C
0x8081_0060 - 0x8081_0064
0x8081_0080
0x8081_0084
0x8081_0088
0x8081_008C
0x8082_xxxx
0x8082_0000
0x8082_0004
0x8082_0008
0x8082_000C
0x8082_0010
0x8082_0014
0x8082_0018
0x8082_001C
0x8082_0020
0x8082_0024
0x8082_0028
0x8082_002C
0x8082_0030
0x8082_0034
0x8082_0038
Address
VIC2VectCntl11
VIC2VectCntl12
VIC2VectCntl13
VIC2VectCntl14
VIC2VectCntl15
VIC2PeriphID0
VIC2PeriphID1
VIC2PeriphID2
VIC2PeriphID3
Timer1Load
Timer1Value
Timer1Control
Timer1Clear
Timer2Load
Timer2Value
Timer2Control
Timer2Clear
Timer3Load
Timer3Value
Timer3Control
Timer3Clear
I2STXClkCfg
I2SRXClkCfg
I2SGlSts
I2SGlCtrl
I2STX0Lft
I2STX0Rt
I2STX1Lft
I2STX1Rt
I2STX2Lft
I2STX2Rt
I2STXLinCtrlData
I2STXCtrl
I2STXWrdLen
I2STX0En
I2STX1En
Register Name
Table 2-8. Internal Register Map (Continued)
TIMER
I2S
Copyright 2007 Cirrus Logic
Vector control 11 Register
Vector control 12 Register
Vector control 13 Register
Vector control 14 Register
Vector control 15 Register
VIC Identification Register bits 7:0
VIC Identification Register bits 15:8
VIC Identification Register bits 23:16
VIC Identification Register bits 31:24
Reserved
Contains the initial value of the timer
Gives the current value of the timer
Provides enable/disable and mode configurations for the timer
Clears an interrupt generated by the timer
Contains the initial value of the timer
Gives the current value of the timer
Provides enable/disable and mode configurations for the timer
Clears an interrupt generated by the timer
Reserved
Contains the initial value of the timer
Gives the current value of the timer
Provides enable/disable and mode configurations for the timer
Clears an interrupt generated by the timer
Transmitter clock configuration Register
Receiver clock configuration Register
I2S Global Status Register. This reflects the status of the 3 RX
FIFOs and the 3 TX FIFOs
I2S Global Control Register
Left Transmit data Register for channel 0
Right Transmit data Register for channel 0
Left Transmit data Register for channel 1
Right Transmit data Register for channel 1
Left Transmit data Register for channel 2
Right Transmit data Register for channel 2
Transmit Line Control Register
Transmit Control Register
Transmit Word Length
TX0 Channel Enable
TX1 Channel Enable
ARM920T Core and Advanced High-Speed Bus (AHB)
Register Description
Timer Registers
I2S Registers
EP93xx User’s Guide
Lock
SW
2-25
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
2