IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 105

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Testbench
Receiver Testbench Examples
Table 6–3. Error Generation Tasks in the Packet Generation Module
Table 6–4. Error Simulation Using the Testbench Module (Part 1 of 2)
December 2010 Altera Corporation
spi_gen.cw2
(cw_type,eops[1:0],sop,
port[7:0],dip4err)
spi_gen.pay (data[15:0])
err_ry_meop
err_ry_msop
err_ry_paddr
err_ry_fifo_oflw
err_rd_dpa
err_rd_abuf_oflw
err_rd_eightn
Error Signal
Task Format
Table 6–4
function by running the packet generation tasks in the testbench module. When
simulating errors on the SPI-4.2 interface, you must turn off error checking on the
testbench interface by using the following tasks:
■
■
■
To disable the missing EOP check on the POS-PHY Level 4 interface:
spi_gen.check_meop = 1’b0;
To disable the missing SOP check on the POS-PHY Level 4 interface:
spi_gen.check_msop = 1’b0;
To disable error checking on the data analyzer interface:
sapmon.checking(1’b0);
Using the pkt2 task, send in packets with error code 3:
spi_gen.pkt2(<port>,/*err*/3,<size>,<pkt_num>);
Using the pkt2 task, send in packets with error code 2:
spi_gen.pkt2(<port>,/*err*/2,<size>,<pkt_num>);
Using the pkt2 task, send in a packet with an address greater than the setting for number of
ports.
Turn off the data analyzer interface:
sapmon.port0.stop;
spi_gen.idles(10);
Send in a large packet:
spi_gen.next_pkt2(<port>,/*err*/0,/*size*/5000);
This error signal can only be asserted on a Stratix GX device. Delay one of the bits of the Rx SPI-
4.2 bus by more than the tolerable amount of 4.5,:
delay.bit_delay(/*rctl*/0, /*rdat*/9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0);
This error signal cannot be simulated with this version of the testbench.
Using the pkt2 task, send in a packet with a missing EOP and a non 16-byte multiple length:
spi_gen.pkt2(<port>,/*err*/3,65,<pkt_num>);
gives examples of how to simulate the 12 error conditions in the MegaCore
Similar to the cw task,
but has separate
arguments for each
control word field.
DIP4 is auto
calculated and
inserted, and it can be
inverted.
Sends a payload data
burst for one cycle.
General Description
Testbench Simulation
cw_type sets the control word type, in accordance with
the POS-PHY4 specification.
eops[1:0] sets the EOP status, in accordance with the
POS-PHY4 specification.
sop sets the SOP status, in accordance with the POS-
PHY4 specification.
port[7:0] sets the port address.
When the dip4_err bit is set, the DIP4 calculation is
inverted.
dat[15:0] sets the payload data bytes.
Input Parameters Description
POS-PHY Level 4 MegaCore Function User Guide
6–5