IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 113

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix A: Start-Up Sequence
Troubleshooting
Table A–1. Start-Up Sequence (Part 2 of 2)
Troubleshooting
December 2010 Altera Corporation
Event
5b
6
Trained —Non-DPA
variations of
receiver MegaCore
functions
Ready
Issues and Tips—Transmitter
Issues and Tips—Receiver
Description
This section provides some troubleshooting issues and tips.
1. The PLL locked signal is not asserted or toggles. Ensure that the input clock jitter is
2. Status channel does not sync. This problem can occur when stat_ts_sync remains
3. The PLL locked signal is not asserted or toggles. Ensure that the input clock jitter is
within the PLL jitter requirements. In some cases, if the PLL locked signal toggles
the PLL must be reset. If so, perform the appropriate steps listed in
page
low, and/or stat_ts_disabled toggles or remains high and/or err_ts_frm
and/or err_ts_dip2 toggles. The following tips may prove useful:
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■
■
■
■
■
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within the PLL jitter requirements. In some cases, if the PLL locked signal toggles,
the PLL must be reset. If so, perform the appropriate steps listed in
page
A single training pattern is required to obtain
lock.
The data path is deskewed and error signals
are valid. stat_rd_rdat_sync is asserted
once the Atlantic buffers are ready and the
DIP-4 out-of-service clears. The receiver is
ready to receive data and transmits valid
status frames.
For 128-bit receiver variations, ensure that the rxsys_clk to rdint_clk ratio is
set according to the receive clock setting in
Ensure that the calendar length and calendar multiplier are set to the same
values in both devices.
Verify timing requirements for the status channel.
Select the clock edge that drives or samples the clock with ctl_ts_statedge
and ctl_rs_statedge.
Verify t
ALTDDIO megafunction keeps on-chip skew to a minimum.
Verify board skew for rsclk/rstat.
Verify the setup and hold times for tstat on tsclk in the transmit MegaCore
function. The ALTDDIO megafunction keeps on-chip skew to a minimum.
Verify that tsclk is operating at the correct frequency.
A–2. Refer to your PLL’s documentation for further information.
A–2. Refer to your PLL’s documentation for further information.
Receiver MegaCore Function
co
for the rsclk and rstat pins in the receiver MegaCore function. The
—
Device correctly receives a good_level
(ctl_ts_sync_good_threshold) of status
frames and asserts stat_ts_sync.
The transmitter is ready to transmit data. It
transmits idles or data.
Table C–1 on page
POS-PHY Level 4 MegaCore Function User Guide
Transmitter MegaCore Function
C–1.
Table A–1 on
Table A–1 on
A–3