IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 119

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Table C–1. rxsys_clk Frequency Restrictions
December 2010 Altera Corporation
32
64
128
Note to
(1) For packet lengths ≤ 16 bytes, C1 = 1.
Width (Bits)
Data Path
Table
C–1:
Restriction
Label
The MegaCore function’s protocol logic and all Atlantic FIFO buffers share a common
clock called rxsys_clk that clocks both the write and read sides of the Atlantic FIFO
buffers.
Restriction (a) is imposed by the SOP alignment block, which moves the SOP for each
packet into the first-byte position. This move slows the pipeline and temporarily fills
up the alignment buffer. If the higher frequency requirement is not met, the alignment
buffer may overflow. To guarantee correct system operation, the smallest expected
packet size should be used, and the assumption that the MegaCore function is
receiving a constant stream of packets is made.
Restriction (b) comes from the status generation. The MegaCore function requires one
clock cycle more than the length of the status frame to generate a status frame. This
cycle is added on the rxsys_clk domain, thus it must be faster than rsclk. If this
requirement is not met, the MegaCore function does not operate correctly,
err_ry_stat_fifo is asserted periodically, and the status generated is invalid. The
worst case is the minimum length status frame which is three cycles long, giving a
ratio of 4/3.
For example, consider a 128-bit MegaCore function with an LVDS data rate of
800 Mbps, using a single port, a calendar length of 1, and a calendar multiple of 1. For
this example, rdint_clk = rsclk = 100 MHz.
For a minimum packet size of 48 bytes, the required frequency for rxsys_clk from
restriction (a) is:
b
a
a
a
C1 = (48 +2) /16 = 3.125
Required rxsys_clk frequency ≥ [Ceiling (3.1251) / 3.125] × 100 = (4/3.125) × 100
= 128 MHz
Table C–1
rxsys_clk frequency ≥ rdint_clk frequency
rxsys_clk frequency ≥ [Ceiling (C1) / C1] × rdint_clk frequency
where C1 = (Packet Length +2)/8
rxsys_clk frequency ≥ (Ceiling (C1, 1) / C1) × rdint_clk frequency
where C1 = (Packet Length +2)/16
rxsys_clk frequency ≥ rsclk × (Status Frame Length + 1)/(Status Frame Length)
shows the rxsys_clk clock frequency restrictions.
C. Optimum Frequency for rxsys_clk
(1)
(1)
Restriction
POS-PHY Level 4 MegaCore Function User Guide