IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 97

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Avalon-MM Interface Register Map
Table 5–10. Avalon-MM Interface Register Map
December 2010 Altera Corporation
0
1
2
3
4
5
6
7
8
9..15
Address
12:0
15:13
0
1
2
3
4
5
7:0
7:0
9:0
9:0
9:0
7:0
—
7:0
Bits
1
1
AOT_ID
BLOCK_ID
HBWR_EN
RSFRM
RESERVED
CALSEL_ACT
SYNC
DISABLED
CALM0
CALM1
CALLEN0
CALLEN1
CALMEM_ADR
CALMEM_DAT0
CALMEM_DAT1
RESERVED
If the hitless bandwidth repositioning (HBWR) register is not enabled, the CALM1,
CALLEN1, CALMEM_DAT registers become reserved.
Only change the CALM0, CALLEN0, CALMEM_DAT0 registers when the DISABLED register is
equal to 1, or when the CALSEL_ACT register is equal to 1. Only change the CALM1,
CALLEN1, CALMEM_DAT1 registers when the DISABLED register is equal to 1, or when the
CALSEL_ACT register is equal to 0.
Name
Read only status
Read only status
Read write control
Read write control
Reserved
Read only status
Read only status
Read only status
Read write control CALM when CALSEL_ACT=0.
Read write control CALM when CALSEL_ACT=1.
Read write control CALLEN when CALSEL_ACT=0.
Read write control CALLEN when CALSEL_ACT=1.
Read write indirect
control
Read write indirect
data
Read write indirect
data
Reserved
Type
AOT code
Block ID
HBWR_EN enables the calendar select word in the status
frame.
RSFRM disables the status finite state machine. This forces
stat_ts_sync low and stat_ts_disabled high at the end
of the current status frame. Regular behavior eventually
resumes after this bit is cleared. The value of the register is
ORed with the ctl_ts_rsfrm input.
This bit resets to one. Therefore, you must reprogram the
calendar and clear this bit whenever the MegaCore function is
reset.
Reserved.
CALSEL_ACT is the active calendar select word. 0='b01,
1='b10
Mirror of stat_ts_sync.
Mirror of stat_ts_disabled.
Refer to CALMEM_DAT0 and CALMEM_DAT1.
If write, then CALMEM_ADR is applied to the write address of
RAM with CALMEM_DAT0 applied to the write data.
If read, then CALMEM_ADR is applied to the read address of
RAM, and resulting read data is captured in CALMEM_DAT0.
If write, then CALMEM_ADR is applied to the write address of
RAM with CALMEM_DAT1 applied to the write data.
If read, then CALMEM_ADR is applied to the read address of
RAM, and resulting read data is captured in CALMEM_DAT1.
Reserved.
POS-PHY Level 4 MegaCore Function User Guide
Description
5–25