IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 137

• Manufacturer Part Number: IPR-POSPHY4
• Description: IP CORE Renewal Of IP-POSPHY4
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix G: Conversion from v2.2.x
Receiver Signals
Table G–1. Receiver Signal Changes (Part 2 of 3)
December 2010 Altera Corporation
err_ry_msopN
err_ry_meopN
stat_ry_mp_erradr
ctl_ry_ae
ctl_ry_af
ctl_ry_fifostatoverride
ctl_ry_extstat_val
ctl_ry_extstat_adr
ctl_ry_extstat
ctl_rs_statedge
ctl_ry_rsfrm
stat_ry_disabled
stat_ry_dip2state
ctl_ry_callen
ctl_ry_calm
stat_ry_calsel
rav_clk
rav_reset_n
rav_address
rav_chipselect
rav_write
rav_read
rav_writedata
rav_readdata
rav_waitrequest
err_rd_dpa
stat_rd_dpa_locked
stat_rd_dpa_lvds_locked
ctl_rd_dpa_force_unlock
stat_rd_rdat_sync
stat_rd_tp_flag
stat_rd_rsv_cw
ctl_rd_dip4_bad_threshold
ctl_rd_dip4_good_threshold
Version 2.4.x and 2.3.x Signal
Name
err_xx_msop
err_xx_meop
stat_xx_mp_erradr
ctl_xx_rxae
ctl_xx_rxaf
ctl_rr_fifostatoverride
ctl_a0_extstat_val
ctl_a0_extstat_adr
ctl_a0_extstat
ctl_rr_statedge
ctl_rr_rsfrm
–
stat_rr_dip2state
ctl_rr_rxcallen
ctl_rr_rxcalm
–
–
–
–
–
–
–
–
–
–
err_rr_dpa
stat_rr_dpa_locked
stat_rr_dpa_lvds_locked
ctl_rr_dpa_force_unlock
stat_rr_rdat_sync
stat_rr_tp_flag
stat_rr_rsv_cw
ctl_rr_dip4_bad_threshold
ctl_rr_dip4_good_threshold
Version 2.2.x Signal Name
In version 2.2.x, these signals are in the
rrefclk domain; in version 2.3.0, these
signals are in the rxsys_clk domain.
No change.
In version 2.2.x, these signals are in the
rrefclk domain; in version 2.3.0, these
signals are in the rxsys_clk domain.
New.
In version 2.2.x, these signals are in the
rrefclk domain; in version 2.3.0, these
signals are in the rxsys_clk domain.
New restrictions. The system does not function
properly if these signals are set incorrectly.
Refer to
details.
New.
New Avalon-MM interface signals. These
signals are present only when Asymmetric Port
Support is turned on. rav_reset_n tied high in
the IP Toolbench top-level file.
No change.
No change.
Reduced to 4-bit only.
POS-PHY Level 4 MegaCore Function User Guide
Table C–1 on page C–1
Notes
for further
G–3