IPR-POSPHY4 Altera, IPR-POSPHY4 Datasheet - Page 126

IP CORE Renewal Of IP-POSPHY4

IPR-POSPHY4

Manufacturer Part Number
IPR-POSPHY4
Description
IP CORE Renewal Of IP-POSPHY4
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-POSPHY4

Software Application
IP CORE, Interface And Protocols, COMMUNICATION
Supported Families
Arria GX, Cyclone, HardCopy, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
POS-PHY Level 4 Interface, Link-Layer/PHY Layer
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
E–2
POS-PHY Level 4 MegaCore Function User Guide
2. Write a value into the CALM0 field, to set the calendar multiplier for calendar 0.
3. Write a 5 into the CALLEN0 field, to set the calendar length to 5 slots for calendar 0.
4. Map the calendar 0 slot numbers to the desired port numbers. The slots are
5. Write a value into the CALM1 field, to set the calendar multiplier for calendar 1.
6. Write a 3 into the CALLEN1 field, to set the calendar length to 3 slots for calendar 1.
7. Map the calendar 1 slot numbers to the desired port numbers:
8. Enable the status channel by writing a 0 to the RSFRM bit, if required.
1
addressed indirectly via the CALMEM_ADR register. Write to the CALMEM_ADR register
first, to set the slot number, and then you can write the port number to the
CALMEM_DAT0 register.
a. Assign port 0 to slot 0:
b. Assign port 3 to slot 1:
c. Assign port 2 to slot 2:
d. Assign port 3 to slot 3:
e. Assign port 0 to slot 4:
a. Assign port 1 to slot 0:
b. Assign port 2 to slot 1:
c. Assign port 3 to slot 2:
Write 0 to CALMEM_ADR.
Write 0 to CALMEM_DAT0.
Write 1 to CALMEM_ADR.
Write 3 to CALMEM_DAT0.
Write 2 to CALMEM_ADR.
Write 2 to CALMEM_DAT0.
Write 3 to CALMEM_ADR.
Write 3 to CALMEM_DAT0.
Write 4 to CALMEM_ADR.
Write 0 to CALMEM_DAT0.
Write 0 to CALMEM_ADR.
Write 1 to CALMEM_DAT1.
Write 1 to CALMEM_ADR.
Write 2 to CALMEM_DAT1.
Write 2 to CALMEM_ADR.
Write 3 to CALMEM_DAT1.
This step is typically only required after reset or power up and prevents
accessing the calendar memories before they are configured.
Appendix E: Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface
December 2010 Altera Corporation
Programming the SPI-4.2 Calendar

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