EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 12

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
Figure 5. APEX 20KC Logic Element
12
labclkena2
Chip-Wide
labclkena1
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
Look-Up
Asynchronous
Clear/Preset/
Clock & Clock
Enable Select
(LUT)
Table
Load Logic
Carry-Out
Carry-In
Chain
Carry
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output.
Cascade-In
Cascade
Chain
Cascade-Out
Synchronous
LAB-wide
Load
Synchronous
Load & Clear
Logic
Synchronous
LAB-wide
Clear
Register Bypass
D
ENA
CLRN
PRN
Packed
Register Select
Q
Programmable
Register
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Altera Corporation