EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 43

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
Advanced I/O Standard Support
APEX 20KC IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
f
For more information on I/O standards supported by APEX 20KC
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
The APEX 20KC device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL at up to 156 Mbps per channel with the addition of external
resistors. In addition, one block within a bank contains circuitry to
support high-speed True-LVDS and LVPECL inputs, and another block
within a bank supports high-speed True-LVDS and LVPECL outputs. The
LVDS blocks support all of the I/O standards. Each I/O bank has its own
VCCIO pins. A single device can support 1.8-V, 2.5-V, and 3.3-V interfaces;
each bank can support a different standard independently. Each bank can
also use a separate V
level so that each bank can support any of the
REF
terminated standards (such as SSTL-3) independently. Within a bank, any
one of the terminated standards can be supported. EP20K400C and larger
APEX 20KC devices support the LVDS interface for data pins (EP20K200C
devices support LVDS clock pins, but not data pins). EP20K400C and
EP20K600C devices support LVDS for data pins at up to 840 Mbps per
channel. EP20K1000C devices support LVDS on 16 channels at up to 750
Mbps.
Each bank can support multiple standards with the same VCCIO for
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIO voltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used for the LVDS I/O standard, they
support all of the other I/O standards.
Figure 28
shows the arrangement
of the APEX 20KC I/O banks.
Altera Corporation
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