EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 68

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
68
t
t
t
t
SU
H
CO
LUT
Table 36. APEX 20KC f
Symbol
LE register setup time before clock
LE register hold time before clock
LE register clock-to-output delay
LUT delay for data-in to data-out
MAX
LE Timing Parameters
Figure 35. Synchronous Bidirectional Pin External Timing
Notes to
(1)
(2)
Tables 36
Table 39
The output enable and input registers are LE registers in the LAB adjacent to the
bidirectional pin. Use the “Output Enable Routing = Single-Pin” option in the
Quartus II software to set the output enable register.
Use the “Decrease Input Delay to Internal Cells = OFF” option in the Quartus II
software to set the LAB-adjacent input register. This maintains a zero hold time for
LAB-adjacent registers while giving a fast, position-independent setup time. Set
“Decrease Input Delay to Internal Cells = ON” and move the input register farther
away from the bidirectional pin for a faster setup time with zero hold time. The
exact position where zero hold occurs with the minimum setup time varies with
device density and speed grade.
Dedicated
Clock
Figure
describes the functional timing parameters.
to
38
35:
describes the f
Output IOE Register
Input Register (1), (2)
OE Register (1)
D
D
D
Parameter
CLRN
CLRN
CLRN
PRN
MAX
PRN
PRN
Q
Q
Q
timing parameters shown in
t
t
XZBIDIR
ZXBIDIR
t
OUTCOBIDIR
t
t
INSUBIDIR
INHBIDIR
Bidirectional Pin
Altera Corporation
Figure
32.