EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 26

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
Figure 14. APEX 20KC Macrocell
26
Interconnect
32 Signals
from Local
Product-
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus II software then selects the most efficient register operation for
each registered function to optimize resource utilization. The Quartus II
software or other synthesis tools can also select the most efficient register
operation automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
Select
Matrix
Term
Parallel Logic
Expanders
(From Other
Macrocells)
ESB-Wide
Clears
2
Clock Enables
ESB-Wide
2
ESB-Wide
Clocks
2
Enable
Clock/
Select
Select
Clear
D
ENA
CLRN
Q
Programmable
Altera Corporation
Register
ESB
Output