EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 33

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

Altera Corporation
Figure 22. ESB in Single-Port Mode
Note
(1)
address[ ]
outclock
outclken
inclken
inclock
data[ ]
wren
Dedicated Clocks
All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
toFigure
4
Dedicated Inputs &
Global Signals
22:
4
Single-Port Mode
The APEX 20KC ESB also supports a single-port mode, which is used
when simultaneous reads and writes are not required. See
Content-Addressable Memory
In APEX 20KC devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12 is stored in address 14, the CAM
outputs 14 when FA12 is driven into it.
D
ENA
D
ENA
Note (1)
Q
Q
Generator
D
ENA
Pulse
Write
APEX 20KC Programmable Logic Device Data Sheet
Q
Data In
Address
Write Enable
RAM/ROM
1,024 × 2
2,048 × 1
Data Out
128 × 16
256 × 8
512 × 4
D
ENA
Q
Figure
To MegaLAB,
FastTrack &
Local
Interconnect
22.
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