EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 48

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

APEX 20KC Programmable Logic Device Data Sheet
48
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the APEX 20KC ClockLock and ClockBoost circuitry will
lock onto the clock during configuration. The circuit will be ready for use
immediately after configuration. In APEX 20KC devices, the clock input
standard is programmable, so the PLL cannot respond to the clock until
the device is configured. The PLL locks onto the input clock as soon as
configuration is complete.
clock specifications.
1
Figure 29. Specifications for the Incoming & Generated Clocks
Note to
(1)
ClockLock
Generated
Clock
The t
nominal output clock period.
Rise and fall times are measured from 10% to 90%.
Input
Clock
I
Figure
parameter refers to the nominal input clock period; the t
For more information on ClockLock and ClockBoost circuitry,
see
Features in APEX
t
Application Note 115: Using the ClockLock and ClockBoost PLL
R
29:
(1)
f
CLK1
t
OUTDUTY
f
CLK4
,
t
f
F
CLK2
(1)
,
t
Devices.
Figure 29
INDUTY
t
t
O
O
t
t
I +
O +
shows the incoming and generated
t
t
INCLKSTB
JITTER
t
O
t
JITTER
O
parameter refers to the
t
Altera Corporation
I +
t
CLKDEV