EP20K400CB652C7 Altera, EP20K400CB652C7 Datasheet - Page 71

• Manufacturer Part Number: EP20K400CB652C7
• Description: APEX 20KC
• Manufacturer: Altera

Altera Corporation
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTl+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
INSUBIDIRPLL
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
ZXBIDIRPLL
Table 41. APEX 20KC External Bidirectional Timing Parameters
Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 1 of 2)
These timing parameters are sample-tested only.
For more information, refer to
Symbol
Tables 40
Symbol
and 41:
Setup time for bidirectional pins with global clock at LAB-adjacent input
register
Hold time for bidirectional pins with global clock at LAB-adjacent input
register
Clock-to-output delay for bidirectional pins with global clock at IOE
register
Synchronous output enable register to output buffer disable delay
Synchronous output enable register to output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB-adjacent input
register
Hold time for bidirectional pins with PLL clock at LAB-adjacent input
register
Clock-to-output delay for bidirectional pins with PLL clock at IOE register
Synchronous output enable register to output buffer disable delay with
PLL
Synchronous output enable register to output buffer enable delay with
PLL
Input adder delay for the LVCMOS I/O standard
Input adder delay for the LVTTL I/O standard
Input adder delay for the 2.5-V I/O standard
Input adder delay for the 1.8-V I/O standard
Input adder delay for the PCI I/O standard
Input adder delay for the GTL+ I/O standard
Input adder delay for the SSTL-3 Class I I/O standard
Input adder delay for the SSTL-3 Class II I/O standard
Input adder delay for the SSTL -2 Class I I/O standard
Input adder delay for the SSTL -2 Class II I/O standard
Tables 42
output standards require test load circuits for AC timing measurements as
shown in
Table
43.
Figures 36
and
43
define the timing delays for each I/O standard. Some
Parameter
Parameter
through 38.
APEX 20KC Programmable Logic Device Data Sheet
Note (1)
Note (1)
Condition
(2)
(2)
(2)
(2)
(2)
(2)
Condition
71